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SN74SSQEB32882ZALR

产品描述JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA 0 to 85
产品类别逻辑    逻辑   
文件大小691KB,共9页
制造商Global Connector Technology
标准
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SN74SSQEB32882ZALR概述

JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test 176-NFBGA 0 to 85

SN74SSQEB32882ZALR规格参数

参数名称属性值
Brand NameTexas Instruments
是否无铅不含铅
是否Rohs认证符合
零件包装代码BGA
包装说明TFBGA, BGA176,11X20,25
针数176
Reach Compliance Codecompliant
ECCN代码EAR99
Factory Lead Time6 weeks
系列S
输入调节STANDARD
JESD-30 代码R-PBGA-B176
JESD-609代码e1
长度13.5 mm
逻辑集成电路类型PLL BASED CLOCK DRIVER
湿度敏感等级3
功能数量1
反相输出次数
端子数量176
实输出次数
最高工作温度85 °C
最低工作温度
封装主体材料PLASTIC/EPOXY
封装代码TFBGA
封装等效代码BGA176,11X20,25
封装形状RECTANGULAR
封装形式GRID ARRAY, THIN PROFILE, FINE PITCH
包装方法TR
峰值回流温度(摄氏度)260
电源1.25/1.5 V
认证状态Not Qualified
座面最大高度1.2 mm
表面贴装YES
温度等级OTHER
端子面层Tin/Silver/Copper (Sn/Ag/Cu)
端子形式BALL
端子节距0.65 mm
端子位置BOTTOM
处于峰值回流温度下的最长时间NOT SPECIFIED
宽度8 mm
Base Number Matches1

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SN74SSQEB32882
www.ti.com
SCAS896-PUB – JUNE 2010
28-Bit to 56-Bit Registered Buffer With Address Parity Test
One Pair to Four Pair Differential Clock PLL Driver
Check for Samples:
SN74SSQEB32882
1
FEATURES
1-to-2 Register Outputs and 1-to-4 Clock Pair
Outputs Support Stacked DDR3 RDIMMs
CKE Powerdown Mode for Optimized System
Power Consumption
1.5V/1.35V/1.25V Phase Lock Loop Clock
Driver for Buffering One Differential Clock Pair
(CK and CK) and Distributing to Four
Differential Outputs
1.5V/1.35V/1.25V CMOS Inputs
Checks Parity on Command and Address
(CS-Gated) Data Inputs
Configurable Driver Strength
Uses Internal Feedback Loop
APPLICATIONS
DDR3 Registered DIMMs up to DDR3-1866
DDR3L Registered DIMMs up to DDR3L-1600
DDR3U Registered DIMMs up to DDR3U-1333
Single-, Dual- and Quad-Rank RDIMM
DESCRIPTION
This JEDEC SSTE32882 28-bit 1:2 or 26-bit 1:2 and 4-bit 1:1 registering clock driver with parity is designed for
operation on DDR3 registered DIMMs with V
DD
of 1.5 V, on DDR3L registered DIMMs with V
DD
of 1.35 V and on
DDR3U registered DIMMs with V
DD
of 1.25 V.
All inputs are 1.5 V, 1.35V and 1.25 V CMOS compatible. All outputs are CMOS drivers optimized to drive DRAM
signals on terminated traces in DDR3 RDIMM applications. The clock outputs Yn and Yn and control net outputs
DxCKEn, DxCSn and DxODTn can be driven with a different strength and skew to optimize signal integrity,
compensate for different loading and equalize signal travel speed.
The SN74SSQEB32882 has two basic modes of operation associated with the Quad Chip Select Enable
(QCSEN) input. When the QCSEN input pin is open (or pulled high), the component has two chip select inputs,
DCS0 and DCS1, and two copies of each chip select output, QACS0, QACS1, QBCS0 and QBCS1. This is the
"QuadCS disabled" mode. When the QCSEN input pin is pulled low, the component has four chip select inputs
DCS[3:0], and four chip select outputs, QCS[3:0]. This is the "QuadCS enabled" mode. Through the remainder of
this specification, DCS[n:0] will indicate all of the chip select inputs, where n=1 for QuadCS disabled, and n=3 for
QuadCS enabled. QxCS[n:0] will indicate all of the chip select outputs.
The device also supports a mode where a single device can be mounted on the back side of a DIMM. If
MIRROR=HIGH, Input Bus Termination (IBT) has to stay enabled for all input signals in this case.
The SN74SSQEB32882 operates from a differential clock (CK and CK). Data are registered at the crossing of
CK going HIGH, and CK going LOW. This data could be either re-driven to the outputs or it could be used to
access device internal control registers.
The input bus data integrity is protected by a parity function. All address and command input signals are added
up and the last bit of the sum is compared to the parity signal delivered by the system at the input PAR_IN one
clock cycle later. If they do not match the device pulls the open drain output ERROUT LOW. The control signals
(DCKE0, DCKE1, DODT0, DODT1, DCS[n:0]) are not part of this computation.
The SN74SSQEB32882 implements different power saving mechanisms to reduce thermal power dissipation and
to support system power down states. By disabling unused outputs the power consumption is further reduced.
The package is optimized to support high density DIMMs. By aligning input and output positions towards DIMM
finger signal ordering and SDRAM ballout the device de-scrambles the DIMM traces allowing low cross talk
design with low interconnect latency.
Edge controlled outputs reduce ringing and improve signal eye opening at the SDRAM inputs.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2010, Texas Instruments Incorporated
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