GS74104ATP/J/X
SOJ, TSOP, FP-BGA
Commercial Temp
Industrial Temp
Features
• Fast access time: 6, 7, 8, 10, 12 ns
• CMOS low power operation: 155/135/120/95/85 mA at
minimum cycle time
• Single 3.3 V power supply
• All inputs and outputs are TTL-compatible
• Fully static operation
• Industrial Temperature Option: –40° to 85°C
• Package line up
J: 400 mil, 32-pin SOJ package
TP: 400 mil, 44-pin TSOP Type II package
X: 6 mm x 10 mm Fine Pitch Ball Grid Array
package
1M x 4
4Mb Asynchronous SRAM
SOJ 1M x 4-Pin Configuraton
A
4
A
3
A
2
A
1
A
0
CE
DQ
1
V
DD
V
SS
DQ
2
WE
A
19
A
18
A
17
A
16
A
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
6, 7, 8, 10, 12 ns
3.3 V V
DD
Center V
DD
and V
SS
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
32-pin
400 mil SOJ
Description
The GS74104A is a high speed CMOS Static RAM organized
as 1,048,576 words by 4 bits. Static design eliminates the need
for external clocks or timing strobes. The GS operates on a
single 3.3 V power supply and all inputs and outputs are TTL-
compatible. The GS74104A is available in 400 mil SOJ, 400
mil TSOP Type-II, and 6 mm x 10 mm FP-BGA packages.
A
5
A
6
A
7
A
8
A
9
OE
DQ
4
V
SS
V
DD
DQ
3
A
10
A
11
A
12
A
13
A
14
NC
FP-BGA 256K x 16 Bump Configuration (Package X)
1
2
3
4
5
6
A
LB
DQ
16
OE
UB
A
0
A
3
A
5
A
17
NC
A
8
A
10
A
13
A
1
A
4
A
6
A
7
A
16
A
9
A
11
A
14
A
2
CE
DQ
2
DQ
4
DQ
5
DQ
7
WE
A
15
NC
DQ
1
DQ
3
V
DD
V
SS
DQ
6
DQ
8
NC
Pin Descriptions
Symbol
A
0
–A
19
DQ
1
–DQ
4
CE
WE
OE
V
DD
V
SS
NC
B
Description
Address input
Data input/output
Chip enable input
Write enable input
Output enable input
+3.3 V power supply
Ground
No connect
C
D
E
F
G
H
DQ
14
DQ
15
V
SS
V
DD
DQ
13
DQ
12
DQ
11
DQ
10
DQ
9
NC
NC
A
12
6 x 10 mm Bump Pitch
Rev: 1.02 3/2002
1/15
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74104ATP/J/X
TSOP-II 1M x 4-Pin Configuration
NC
NC
NC
A
4
A
3
A
2
A
1
A
0
CE
DQ
1
V
DD
V
SS
DQ
2
WE
A
19
A
18
A
17
A
16
A
15
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
NC
NC
NC
A
5
A
6
A
7
A
8
A
9
OE
DQ
4
V
SS
V
DD
DQ
3
A
10
A
11
A
12
A
13
A
14
NC
NC
NC
NC
44-pin
400 mil TSOP II
34
33
32
31
30
29
28
27
26
25
24
23
Block Diagram
A
0
Address
Input
Buffer
Row
Decoder
Memory Array
A
19
CE
WE
OE
Column
Decoder
Control
I/O Buffer
DQ
1
DQ
4
Rev: 1.02 3/2002
2/15
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74104ATP/J/X
Truth Table
CE
H
L
L
L
Note: X: “H” or “L”
OE
X
L
X
H
WE
X
H
L
H
DQ
1
to DQ
8
Not Selected
Read
Write
High Z
V
DD
Current
ISB
1
, ISB
2
I
DD
Absolute Maximum Ratings
Parameter
Supply Voltage
Input Voltage
Output Voltage
Allowable power dissipation
Storage temperature
Symbol
V
DD
V
IN
V
OUT
PD
T
STG
Rating
–0.5 to +4.6
–0.5 to V
DD
+0.5
(≤ 4.6 V max.)
–0.5 to V
DD
+0.5
(≤ 4.6 V max.)
0.7
–55 to 150
Unit
V
V
V
W
o
C
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Rec-
ommended Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device
reliability.
Rev: 1.02 3/2002
3/15
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74104ATP/J/X
Recommended Operating Conditions
Parameter
Supply Voltage for -7/-8/-10/-12
Supply Voltage for -6
Input High Voltage
Input Low Voltage
Ambient Temperature,
Commercial Range
Ambient Temperature,
Industrial Range
Symbol
V
DD
V
DD
V
IH
V
IL
T
Ac
T
A
I
Min
3.0
3.135
2.0
–0.3
0
–40
Typ
3.3
3.3
—
—
—
—
Max
3.6
3.6
V
DD
+0.3
0.8
70
85
Unit
V
V
V
V
o
C
o
C
Notes:
1. Input overshoot voltage should be less than V
DD
+2 V and not exceed 20 ns.
2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns.
Capacitance
Parameter
Input Capacitance
Output Capacitance
Symbol
C
IN
C
OUT
Test Condition
V
IN
= 0 V
V
OUT
= 0 V
Max
5
7
Unit
pF
pF
Notes:
1. Tested at T
A
= 25°C, f = 1 MHz
2. These parameters are sampled and are not 100% tested.
DC I/O Pin Characteristics
Parameter
Input Leakage
Current
Output Leakage
Current
Output High Voltage
Output Low Voltage
Symbol
I
IL
I
LO
V
OH
V
OL
Test Conditions
V
IN
= 0 to V
DD
Output High Z
V
OUT
= 0 to V
DD
I
OH
= –4mA
I
LO
= +4mA
Min
– 1 uA
–1 uA
2.4
—
Max
1 uA
1 uA
—
0.4 V
Rev: 1.02 3/2002
4/15
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
GS74104ATP/J/X
Power Supply Currents
Parameter Symbol Test Conditions
CE
≤
V
IL
All other inputs
≥
V
IH
or
≤
V
IL
Min. cycle time
I
OUT
= 0 mA
CE
≥
V
IH
All other inputs
≥
V
IH
or
≤V
IL
Min. cycle time
CE
≥
V
DD
- 0.2V
All other inputs
≥
V
DD
- 0.2V or
≤
0.2V
0 to 70°C
6 ns
7 ns
8 ns
10 ns
12 ns
6 ns
7 ns
–40 to 85°C
8 ns
10 ns
12 ns
Operating
Supply
Current
I
DD
155 mA 135 mA 120 mA
95 mA
85 mA
165 mA 145 mA 130 mA 105 mA
95 mA
Standby
Current
I
SB1
40 mA
35 mA
30 mA
25 mA
22 mA
50 mA
45 mA
40 mA
35 mA
32 mA
Standby
Current
I
SB2
10 mA
20 mA
AC Test Conditions
Parameter
Input high level
Input low level
Input rise time
Input fall time
Input reference level
Output reference level
Output load
Conditions
V
IH
= 2.4 V
V
IL
= 0.4 V
tr = 1 V/ns
tf = 1 V/ns
1.4 V
1.4 V
Fig. 1& 2
Output Load 1
DQ
50Ω
VT = 1.4 V
30pF
1
Output Load 2
3.3 V
DQ
5pF
1
589Ω
434Ω
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in
Fig. 1
unless otherwise noted.
3. Output load 2 for t
LZ
, t
HZ
, t
OLZ
and t
OHZ
Rev: 1.02 3/2002
5/15
© 2001, Giga Semiconductor, Inc.
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
