Section I. Stratix Device
Family Data Sheet
This section provides the data sheet specifications for Stratix
®
devices.
They contain feature definitions of the internal architecture,
configuration and JTAG boundary-scan testing information, DC
operating conditions, AC timing parameters, a reference to power
consumption, and ordering information for Stratix devices.
This section contains the following chapters:
■
■
■
■
■
Chapter 1, Introduction
Chapter 2, Stratix Architecture
Chapter 3, Configuration & Testing
Chapter 4, DC & Switching Characteristics
Chapter 5, Reference & Ordering Information
Revision History
Chapter
1
The table below shows the revision history for
Chapters 1
through
5.
Date/Version
July 2005, v3.2
September 2004, v3.1
April 2004, v3.0
●
●
●
●
●
●
Changes Made
Minor content changes.
Updated
Table 1–6 on page 1–5.
Main section page numbers changed on first page.
Changed PCI-X to PCI-X 1.0 in
“Features” on page 1–2.
Global change from SignalTap to SignalTap II.
The DSP blocks in
“Features” on page 1–2
provide dedicated
implementation of multipliers that are now “faster than 300 MHz.”
Updated -5 speed grade device information in Table 1-6.
Add -8 speed grade device information.
Format changes throughout chapter.
January 2004, v2.2
October 2003, v2.1
July 2003, v2.0
●
●
●
Altera Corporation
Section I–1
Stratix Device Family Data Sheet
Stratix Device Handbook, Volume 1
Chapter
2
Date/Version
July 2005 v3.2
●
●
●
Changes Made
Added
“Clear Signals”
section.
Updated
“Power Sequencing & Hot Socketing”
section.
Format changes.
Updated fast regional clock networks description on
page 2–73.
Deleted the word preliminary from the “specification for the maximum
time to relock is 100 µs” on
page 2–90.
Added information about differential SSTL and HSTL outputs in
“External Clock Outputs” on page 2–92.
Updated notes in
Figure 2–55 on page 2–93.
Added information about
m
counter to
“Clock Multiplication &
Division” on page 2–101.
Updated Note 1 in
Table 2–58 on page 2–101.
Updated description of
“Clock Multiplication & Division” on
page 2–88.
Updated
Table 2–22 on page 2–102.
Added references to AN 349 and AN 329 to
“External RAM
Interfacing” on page 2–115.
Table 2–25 on page 2–116:
updated the table, updated Notes 3 and
4. Notes 4, 5, and 6, are now Notes 5, 6, and 7, respectively.
Updated
Table 2–26 on page 2–117.
Added information about PCI Compliance to
page 2–120.
Table 2–32 on page 2–126:
updated the table and deleted Note 1.
Updated reference to device pin-outs now being available on the web
on
page 2–130.
Added Notes 4 and 5 to
Table 2–36 on page 2–130.
Updated Note 3 in
Table 2–37 on page 2–131.
Updated Note 5 in
Table 2–41 on page 2–135.
Added note 3 to rows 11 and 12 in
Table 2–18.
Deleted “Stratix and Stratix GX Device PLL Availability” table.
Added I/O standards row in
Table 2–28
that support max and min
strength.
Row
clk [1,3,8,10]
was removed from
Table 2–30.
Added checkmarks in Enhanced column for LVPECL, 3.3-V PCML,
LVDS, and HyperTransport technology rows in
Table 2–32.
Removed the Left and Right I/O Banks row in
Table 2–34.
Changed
RCLK
values in
Figures 2–50
and
2–51.
External RAM Interfacing section replaced.
Added 672-pin BGA package information in
Table 2–37.
Removed support for series and parallel on-chip termination.
Termination Technology renamed differential on-chip termination.
Updated the number of channels per PLL in Tables 2-38 through 2-
42.
Updated
Figures 2–65
and
2–67.
Updated DDR I information.
Updated
Table 2–22.
Added
Tables 2–25, 2–29, 2–30,
and
2–72.
Updated
Figures 2–59, 2–65,
and
2–67.
Updated the Lock Detect section.
September 2004, v3.1
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
April 2004, v3.0
●
●
●
●
●
●
●
●
November 2003, v2.2
●
●
●
●
●
October 2003, v2.1
●
●
●
●
●
Section I–2
Altera Corporation
Stratix Device Family Data Sheet
Chapter
2
Date/Version
July 2003, v2.0
●
●
●
●
●
●
●
●
●
●
●
●
Changes Made
Added reference on page 2-73 to Figures 2-50 and 2-51 for
RCLK
connections.
Updated ranges for EPLL post-scale and pre-scale dividers on page
2-85.
Updated PLL Reconfiguration frequency from 25 to 22 MHz on page
2-87.
New requirement to assert are set signal each PLL when it has to re-
acquire lock on either a new clock after loss of lock (page 2-96).
Updated max input frequency for
CLK[1,3,8,10]
from 462 to 500,
Table 2-24.
Renamed impedance matching to series termination throughout.
Updated naming convention for DQS pins on page 2-112 to match pin
tables.
Added DDR SDRAM Performance Specification on page 2-117.
Added external reference resistor values for terminator technology
(page 2-136).
Added Terminator Technology Specification on pages 2-137 and 2-
138.
Updated Tables 2-45 to 2-49 to reflect PLL cross-bank support for
high speed differential channels at full speed.
Wire bond package performance specification for “high” speed
channels was increased to 624 Mbps from 462 Mbps throughout
chapter.
Updated
“Operating Modes”
section.
Updated
“Temperature Sensing Diode”
section.
Updated
“IEEE Std. 1149.1 (JTAG) Boundary-Scan Support”
section.
Updated
“Configuration”
section.
Updated limits for JTAG chain of devices.
Added new section,
“Stratix Automated Single Event Upset (SEU)
Detection” on page 3–12.
Updated description of
“Custom-Built Circuitry” on page 3–13.
No new changes in
Stratix Device Handbook
v2.0.
Added
Table 4–135.
Updated
Tables 4–6
and
4–30.
Updated
Tables 4–103
through
4–108.
Updated
Tables 4–114
through
4–124.
Updated
Table 4–129.
Added
Table 4–130.
3
July 2005, v1.3
●
●
●
●
January 2005, v1.2
September 2004, v1.1
●
●
●
April 2003, v1.0
4
January 2006, v3.4
July 2005, v3.3
●
●
●
●
●
●
●
Altera Corporation
Section I–3
Stratix Device Family Data Sheet
Stratix Device Handbook, Volume 1
Chapter
4
Date/Version
January 2005, 3.2
September 2004, v3.1
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
Changes Made
Updated rise and fall input values.
Updated Note 3 in
Table 4–8 on page 4–4.
Updated
Table 4–10 on page 4–6.
Updated
Table 4–20 on page 4–12
through
Table 4–23 on
page 4–13.
Added rows V
IL(AC)
and V
IH(AC)
to each table.
Updated
Table 4–26 on page 4–14
through
Table 4–29 on
page 4–15.
Updated
Table 4–31 on page 4–16.
Updated description of
“External Timing Parameters” on page 4–33.
Updated
Table 4–36 on page 4–20.
Added signals t
OUTCO
, T
XZ
, and T
ZX
to
Figure 4–4 on page 4–33.
Added rows t
M512CLKENSU
and t
M512CLKENH
to
Table 4–40 on
page 4–24.
Added rows t
M4CLKENSU
and t
M4CLKENH
to
Table 4–41 on page 4–24.
Updated Note 2 in
Table 4–54 on page 4–35.
Added rows t
MRAMCLKENSU
and t
MRAMCLKENH
to
Table 4–42 on
page 4–25.
Updated
Table 4–46 on page 4–29.
Updated
Table 4–47 on page 4–29.
Section I–4
Altera Corporation
Stratix Device Family Data Sheet
Chapter
4
Date/Version
●
●
●
●
Changes Made
Table 4–48 on page 4–30:
added rows t
M512CLKSENSU
and t
M512CLKENH
,
and updated symbol names.
Updated power-up current (ICCINT) required to power a Stratix
device on
page 4–17.
Updated
Table 4–37 on page 4–22
through
Table 4–43 on
page 4–27.
Table 4–49 on page 4–31:
added rows t
M4KCLKENSU
, t
M4KCLKENH
,
t
M4KBESU
, and t
M4KBEH,
deleted rows t
M4KRADDRASU
and t
M4KRADDRH
, and
updated symbol names.
Table 4–50 on page 4–31:
added rows t
MRAMCLKENSU
, t
MRAMCLKENH
,
t
MRAMBESU
, and t
MRAMBEH
, deleted rows t
MRAMADDRASU
and
t
MRAMRADDRH
, and updated symbol names.
Table 4–52 on page 4–34:
updated table, deleted “Conditions”
column, and added rows t
XZ
and t
ZX
.
Table 4–52 on page 4–34:
updated table, deleted “Conditions”
column, and added rows t
XZ
and t
ZX
.
Table 4–53 on page 4–34:
updated table and added rows t
XZPLL
and
t
ZXPLL
.
Updated Note 2 in
Table 4–53 on page 4–34.
Table 4–54 on page 4–35:
updated table, deleted “Conditions”
column, and added rows t
XZPLL
and t
ZXPLL
.
Updated Note 2 in
Table 4–54 on page 4–35.
Deleted Note 2 from
Table 4–55 on page 4–36
through
Table 4–66 on
page 4–41.
Updated
Table 4–55 on page 4–36
through
Table 4–96 on
page 4–56.
Added rows T
XZ
, T
ZX
, T
XZPLL
, and T
ZXPLL.
Added Note 4 to
Table 4–101 on page 4–62.
Deleted Note 1 from
Table 4–67 on page 4–42
through
Table 4–84 on
page 4–50.
Added new section
“I/O Timing Measurement Methodology” on
page 4–60.
Deleted Note 1 from
Table 4–67 on page 4–42
through
Table 4–84 on
page 4–50.
Deleted Note 2 from
Table 4–85 on page 4–51
through
Table 4–96 on
page 4–56.
Added Note 4 to
Table 4–101 on page 4–62.
Table 4–102 on page 4–64:
updated table and added Note 4.
Updated description of
“External I/O Delay Parameters” on
page 4–66.
Added Note 1 to
Table 4–109 on page 4–73
and
Table 4–110 on
page 4–74.
Updated
Table 4–103 on page 4–66
through
Table 4–110 on
page 4–74.
Deleted Note 2 from
Table 4–103 on page 4–66
through
Table 4–106
on page 4–69.
Added new paragraph about output adder delays on
page 4–68.
Updated
Table 4–110 on page 4–74.
Added Note 1 to
Table 4–111
through
Table 4–113 on page 4–75.
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
●
Altera Corporation
Section I–5
模拟与混合信号
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
