The CY7C1049CV33 is a high-performance CMOS Static
RAM organized as 524,288 words by 8 bits. Easy memory
expansion is provided by an active LOW Chip Enable (CE), an
active LOW Output Enable (OE), and three-state drivers.
Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O
pins (I/O
0
through I/O
7
) is then written into the location
specified on the address pins (A
0
through A
18
).
Reading from the device is accomplished by taking Chip
Enable (CE) and Output Enable (OE) LOW while forcing Write
Enable (WE) HIGH. Under these conditions, the contents of
the memory location specified by the address pins will appear
on the I/O pins.
The eight input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
HIGH), the outputs are disabled (OE HIGH), or during a Write
operation (CE LOW, and WE LOW).
The CY7C1049CV33 is available in standard 400-mil-wide
36-pin SOJ package and 44-pin TSOP II package with center
power and ground (revolutionary) pinout.
Logic Block Diagram
Pin Configuration
SOJ
Top View
TSOP II
Top View
NC
A
18
A
17
A
16
A
15
OE
I/O
7
I/O
6
GND
V
CC
I/O
5
I/O
4
A
14
A
13
A
12
A
11
A
10
NC
I/O
0
INPUT BUFFER
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
I/O
1
ROW DECODER
I/O
2
SENSE AMPS
512K x 8
ARRAY
I/O
3
I/O
4
I/O
5
CE
WE
OE
COLUMN
DECODER
POWER
DOWN
I/O
6
I/O
7
A
0
A
1
A
2
A
3
A
4
CE
I/O
0
I/O
1
V
CC
GND
I/O
2
I/O
3
WE
A
5
A
6
A
7
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
NC
A
0
A
1
A
2
A
3
A
4
CE
I/O
0
I/O
1
V
CC
V
SS
I/O
2
I/O
3
WE
A
5
A
6
A
7
A
8
A
9
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
A
18
A
17
A
16
A
15
OE
I/O
7
I/O
6
V
SS
V
CC
I/O
5
I/O
4
A
14
A
13
A
12
A
11
A
10
NC
NC
NC
Notes:
1. For guidelines on SRAM system design, please refer to the
System Design Guidelines
Cypress application note, available on the internet at www.cypress.com.
A
11
A
12
A
13
A
14
A
15
A
16
A
17
A
18
Cypress Semiconductor Corporation
Document #: 38-05006 Rev. *E
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised March 29, 2005
CY7C1049CV33
Selection Guide
-8
Maximum Access Time
Maximum Operating Current
Commercial
Industrial
Automotive
Maximum CMOS Standby Current Commercial / Industrial
Automotive
Shaded areas contain advance information.
-10
10
90
100
-
10
-
-12
12
85
95
-
10
-
-15
15
80
90
95
10
15
-20
20
80
90
-
10
-
Unit
ns
mA
mA
mA
mA
mA
8
100
110
-
10
-
Pin Definitions
Pin Name
A
0
–A
18
I/O
0
–I/O
7
NC
[2]
36-SOJ
Pin Number
44 TSOP-II
Pin Number
I/O Type
Input
Description
Address Inputs used to select one of the address locations.
1–5,14–18,
3–7,16–20,
20–24,32–35 26–30,38–41
7,8,11,12,25,
26,29,30
19,36
9,10,13,14,
31,32,35,36
1,2,21,22,23,
24,25,42,43,
44
15
8
37
Input/Output
Bidirectional Data I/O lines.
Used as input or output lines
depending on operation
No Connect
No Connects.
This pin is not connected to the die
WE
CE
OE
13
6
31
Input/Control
Write Enable Input, active LOW.
When selected LOW, a WRITE is
conducted. When selected HIGH, a READ is conducted.
Input/Control
Chip Enable Input, active LOW.
When LOW, selects the chip. When
HIGH, deselects the chip.
Input/Control
Output Enable, active LOW.
Controls the direction of the I/O pins.
When LOW, the I/O pins are allowed to behave as outputs. When
deasserted HIGH, I/O pins are three-stated, and act as input data
pins.
Ground
Ground for the device.
Should be connected to ground of the
system.
V
SS
, GND
V
CC
10,28
9,27
12,34
11,33
Power Supply
Power Supply inputs to the device.
Notes:
2. NC pins are not connected on the die.
Document #: 38-05006 Rev. *E
Page 2 of 11
CY7C1049CV33
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on V
CC
to Relative GND
[3]
–0.5V to +4.6VDC
Voltage Applied to Outputs
in High-Z State
[3]
....................................–0.5V to V
CC
+ 0.5V
Input Voltage
[3]
...................................... –0.5V to V
CC
+ 0.5V
Current into Outputs (LOW)......................................... 20 mA
Operating Range
Range
Commercial
Industrial
Automotive
Ambient Temperature
0°C to +70°C
–40°C to +85°C
–40°C to +125°C
V
CC
3.3V
±
0.3V
Electrical Characteristics
Over the Operating Range
-8
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
I
SB1
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[3]
Input Load Current
Output Leakage
Current
V
CC
Operating
Supply Current
Automatic CE
Power-down Current
—TTL Inputs
Automatic CE
Power-down Current
—CMOS Inputs
GND < V
I
< V
CC
GND < V
OUT
< V
CC
,
Output Disabled
V
CC
= Max.,
f = f
MAX
= 1/t
RC
Max. V
CC
, CE > V
IH
;
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Max. V
CC
,
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V,
or V
IN
< 0.3V, f = 0
Com’l/Ind’l
Com’l/Ind’l
Com’l
Ind’l
Com’l/Ind’l
Test Conditions
V
CC
= Min.; I
OH
= –4.0 mA
V
CC
= Min.,; I
OL
= 8.0 mA
2.0
–0.3
–1
–1
Min.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
100
110
40
2.0
–0.3
–1
–1
Max.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
90
100
40
2.0
–0.3
–1
–1
-10
Min.
Max.
2.4
0.4
V
CC
+ 0.3
0.8
+1
+1
85
95
40
-12
Min.
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
I
SB2
Com’l/Ind’l
10
10
10
mA
Electrical Characteristics
Over the Operating Range
-15
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[3]
Input Load Current
Output Leakage
Current
V
CC
Operating
Supply Current
GND < V
I
< V
CC
GND < V
OUT
< V
CC
,
Output Disabled
V
CC
= Max.,
f = f
MAX
= 1/t
RC
Com’l / Ind’l
Automotive
Com’l / Ind’l
Automotive
Com’l
Ind’l
Automotive
Note:
3. V
IL
(min.) = –2.0V and V
IH
(max) = V
CC
+ 0.5V for pulse durations of less than 20 ns.
-20
Max.
0.4
Min.
2.4
0.4
2.0
–0.3
–1
-
–1
-
V
CC
+ 0.3
0.8
+1
-
+1
-
80
90
-
Max.
Unit
V
V
V
V
µA
µA
µA
µA
mA
mA
mA
Test Conditions
V
CC
= Min.; I
OH
= –4.0 mA
V
CC
= Min.,; I
OL
= 8.0 mA
Min.
2.4
2.0
–0.3
–1
–20
–1
–20
V
CC
+ 0.3
0.8
+1
+20
+1
+20
80
90
95
Document #: 38-05006 Rev. *E
Page 3 of 11
CY7C1049CV33
Electrical Characteristics
Over the Operating Range (continued)
-15
Parameter
I
SB1
Description
Automatic CE
Power-down Current
—TTL Inputs
Automatic CE
Power-down Current
—CMOS Inputs
Test Conditions
Max. V
CC
, CE > V
IH
;
V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Max. V
CC
,
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V,
or V
IN
< 0.3V, f = 0
Com’l / Ind’l
Automotive
Com’l/Ind’l
Automotive
Min.
Max.
40
45
10
15
Min.
-20
Max.
40
-
10
-
Unit
mA
mA
mA
mA
I
SB2
Thermal Resistance
[4]
Parameter
Description
Thermal Resistance
(Junction to Ambient)
Thermal Resistance
(Junction to Case)
Test Conditions
Test conditions follow
standard test methods
and procedures for
measuring thermal
impedance, per EIA /
JESD51.
36-pin SOJ 36-pin SOJ 44-TSOP-II 44-TSOP-II
(Non Pb-Free) (Pb-Free) (Non Pb-Free) (Pb-Free) Unit
46.51
18.8
46.51
18.8
41.66
10.56
41.66
10.56
°C/W
°C/W
Θ
JA
Θ
JC
Capacitance
[4]
Parameter
C
IN
C
OUT
Description
Input Capacitance
I/O Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 3.3V
Max.
8
8
Unit
pF
pF
AC Test Loads and Waveforms
[5]
8-, 10-ns devices:
OUTPUT
50Ω
* CAPACITIVE LOAD CONSISTS
OF ALL COMPONENTS OF THE
TEST ENVIRONMENT
1.5V
12-, 15-, 20-ns devices:
Z = 50Ω
3.3V
R 317Ω
30 pF*
OUTPUT
30 pF
R2
351Ω
(a)
High-Z characteristics:
3.0V
90%
GND
10%
ALL INPUT PULSES
90%
10%
3.3V
OUTPUT
5 pF
(b)
R 317Ω
R2
351Ω
Rise Time: 1 V/ns
(c)
Fall Time: 1 V/ns
(d)
Notes:
4. Tested initially and after any design or process changes that may affect these parameters.
5. AC characteristics (except High-Z) for all 8-ns and 10-ns parts are tested using the load conditions shown in Figure (a). All other speeds are tested using the
Thevenin load shown in Figure (b). High-Z characteristics are tested for all speeds using the test load shown in Figure (d).
Document #: 38-05006 Rev. *E
Page 4 of 11
CY7C1049CV33
AC Switching Characteristics
Over the Operating Range
[6]
-8
Parameter
Read Cycle
t
power[7]
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
V
CC
(typical) to the first access
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z
OE HIGH to High-Z
[8, 9]
CE LOW to Low-Z
[9]
CE HIGH to High-Z
[8, 9]
CE LOW to Power-up
CE HIGH to Power-down
Write Cycle Time
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE HIGH to Low-Z
[9]
WE LOW to High-Z
[8, 9]
8
6
6
0
0
6
4
0
3
4
0
8
10
7
7
0
0
7
5
0
3
5
3
4
0
10
12
8
8
0
0
8
6
0
3
6
0
4
3
5
0
12
3
8
4
0
5
3
6
1
8
8
3
10
5
0
6
1
10
10
3
12
6
1
12
12
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
Min.
-10
Max.
Min.
-12
Max.
Unit
Write Cycle
[10, 11]
Shaded areas contain advance information.
AC Switching Characteristics
Over the Operating Range
[6]
-15
Parameter
Read Cycle
t
power[7]
t
RC
t
AA
t
OHA
t
ACE
t
DOE
V
CC
(typical) to the first access
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
1
15
15
3
15
7
1
20
20
3
20
8
µs
ns
ns
ns
ns
ns
Description
Min.
Max.
Min.
-20
Max.
Unit
Notes:
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
7. t
POWER
gives the minimum amount of time that the power supply should be at stable, typical V
CC
values until the first memory access can be performed.
8. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
9. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
10. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of either
of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the Write.
11. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
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