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TLV1704-SEP
SLOSE29 – NOVEMBER 2018
TLV1704-SEP 2.2-V to 36-V, Radiation Hardened microPower Quad Comparator
in Space Enhanced Plastic
1 Features
•
•
1
2 Applications
•
•
•
•
•
•
•
Support Low Earth Orbit Space Applications
Overvoltage and Undervoltage Detectors
Satellite Telemetry and Telecommand for On-
board Data Handling
Window Comparators
Overcurrent Detectors
Zero-Crossing Detectors
System Monitoring for Space
•
•
•
•
•
•
•
•
VID V62/18613
Radiation Hardened
– Single Event Latch-up (SEL) Immune to 43
MeV-cm
2
/mg at 125°C
– ELDRS Free to 30 krad(Si)
– Total Ionizing Dose (TID) RLAT for Every
Wafer Lot up to 20 krad(Si)
Space Enhanced Plastic
– Controlled Baseline
– Gold Wire
– NiPdAu Lead Finish
– One Assembly and Test Site
– One Fabrication Site
– Available in Military (–55°C to 125°C)
Temperature Range
– Extended Product Life Cycle
– Extended Product-Change Notification
– Product Traceability
– Enhanced Mold Compound for Low
Outgassing
Supply Range: 2.2 V to 36 V or ±1.1 V to ±18 V
Low Quiescent Current: 55 µA per Comparator
Input Common-Mode Range Includes Both Rails
Low Propagation Delay: 560 ns
Low Input Offset Voltage: 300 µV
Open Collector Outputs:
– Up to 36 V Above Negative Supply Regardless
of Supply Voltage
Small Packages:
– Quad: TSSOP-14
TLV1704-SEP as a Window Comparator
3 Description
The TLV1704-SEP (Quad) device offers a wide
supply range, rail-to-rail inputs, low quiescent current,
and low propagation delay. All these features come in
industry-standard, extremely-small packages, making
these devices the best general-purpose comparators
available.
The open collector output offers the advantage of
allowing the output to be pulled to any voltage rail up
to 36 V above the negative power supply, regardless
of the TLV1704-SEP supply voltage.
The device is a microPower comparator. Low input
offset voltage, low input bias currents, low supply
current, and open-collector configuration make the
TLV1704-SEP device flexible enough to handle
almost any application, from simple voltage detection
to driving a single relay.
Device Information
(1)
PART NUMBER
TLV1704AMPWTPSEP
TLV1704AMPWPSEP
GRADE
20 krad(Si) RLAT
PACKAGE
TSSOP (14)
(1) For all available packages, see the package option addendum
at the end of the data sheet.
Stable Propagation Delay vs Temperature
1200
r18
V Low-to-High
r18
V High-to-Low
2.2 V Low-to-High
2.2 V High-to-Low
1000
Propagation Delay (s)
800
600
400
200
-55
-35
-15
5
25
45
65
Temperature (qC)
85
105
125
D001
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TLV1704-SEP
SLOSE29 – NOVEMBER 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features
..................................................................
Applications
...........................................................
Description
.............................................................
Revision History.....................................................
Pin Configuration and Functions
.........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
6.7
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Switching Characteristics ..........................................
Typical Characteristics ..............................................
1
1
1
2
3
4
4
4
4
4
5
5
6
7.4 Device Functional Modes........................................
10
8
Application and Implementation
........................
11
8.1 Application Information............................................
11
8.2 Typical Application .................................................
11
9 Power Supply Recommendations......................
12
10 Layout...................................................................
13
10.1 Layout Guidelines .................................................
13
10.2 Layout Example ....................................................
13
11 Device and Documentation Support
.................
14
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
14
14
14
14
14
14
7
Detailed Description
..............................................
9
7.1 Overview ...................................................................
9
7.2 Functional Block Diagram .........................................
9
7.3 Feature Description.................................................
10
12 Mechanical, Packaging, and Orderable
Information
...........................................................
15
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
November 2018
REVISION
*
NOTES
Initial release.
2
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Copyright © 2018, Texas Instruments Incorporated
TLV1704-SEP
www.ti.com
SLOSE29 – NOVEMBER 2018
5 Pin Configuration and Functions
TLV1704-SEP PW Package
14-Pin TSSOP
Top View
2OUT
1OUT
V+
1IN±
1IN+
2IN±
2IN+
1
2
3
4
5
6
7
14 3OUT
13 4OUT
12 V-
11 4IN+
10 4IN±
9
8
3IN+
3IN±
Pin Functions
PIN
NAME
IN+
1IN+
2IN+
3IN+
4IN+
IN–
1IN–
2IN–
3IN–
4IN–
OUT
1OUT
2OUT
3OUT
4OUT
V+
V–
NO.
—
5
7
9
11
—
4
6
8
10
—
2
1
14
13
3
12
I/O
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
—
—
Noninverting input.
Noninverting input, channel 1.
Noninverting input, channel 2.
Noninverting input, channel 3.
Noninverting input, channel 4.
Inverting input.
Inverting input, channel 1.
Inverting input, channel 2.
Inverting input, channel 3.
Inverting input, channel 4.
Output.
Output, channel 1.
Output, channel 2.
Output, channel 3.
Output, channel 4.
Positive (highest) power supply.
Negative (lowest) power supply.
DESCRIPTION
Copyright © 2018, Texas Instruments Incorporated
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TLV1704-SEP
SLOSE29 – NOVEMBER 2018
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
Supply voltage
Signal input pins
Output short-circuit
(3)
MAX
40 (±20)
(V
S
+) + 0.5
±10
Continuous
UNIT
V
V
mA
mA
°C
°C
Voltage
(2)
(V
S
–) – 0.5
Current
(2)
–55
–65
Operating Junction temperature, T
J
Storage temperature, T
stg
(1)
(2)
(3)
125
150
Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating
Conditions
is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
Short-circuit to ground; one comparator per package.
6.2 ESD Ratings
VALUE
V
(ESD)
(1)
Electrostatic discharge
Human-body model (HBM), per AEC Q100-002
(1)
UNIT
V
±1000
±1000
Charged-device model (CDM), per AEC Q100-011
AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Supply voltage V
S
= (V
S
+) – (V
S
–)
Specified temperature
2.2 (±1.1)
–55
NOM
MAX
36 (±18)
125
UNIT
V
°C
6.4 Thermal Information
TLV1704-SEP
THERMAL METRIC
(1)
R
θJA
R
θJC(top)
R
θJB
ψ
JT
ψ
JB
R
θJC(bot)
(1)
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
PW (TSSOP)
14 PINS
128.1
56.5
69.9
9.1
69.3
N/A
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
UNIT
For more information about traditional and new thermal metrics, see the
Semiconductor and IC Package Thermal Metrics
application
report.
4
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TLV1704-SEP
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SLOSE29 – NOVEMBER 2018
6.5 Electrical Characteristics
at T
A
= –55°C to 125°C, V
S
= 2.2 V to 36 V, C
L
= 15 pF, R
PULLUP
= 5.1 kΩ, V
CM
= V
S
/ 2, and V
S
= V
PULLUP
(unless otherwise
noted)
PARAMETER
OFFSET VOLTAGE
T
A
= 25°C, V
S
= 2.2 V
V
OS
dV
OS
/dT
PSRR
Input offset voltage
T
A
= 25°C, V
S
= 36 V
T
A
= –55°C to 125°C
Input offset voltage drift
Power-supply rejection ratio
T
A
= –55°C to 125°C
T
A
= 25°C
T
A
= –55°C to 125°C
T
A
= –55°C to 125°C
T
A
= 25°C
T
A
= –55°C to 125°C
T
A
= 25°C
0.5
See
Typical Characteristics
(V–)
±4
15
20
±0.5
±0.3
±3.5
±2.5
±5.5
±20
100
mV
mV
mV
μV/°C
μV/V
μV/V
TEST CONDITIONS
MIN
TYP
MAX
UNIT
INPUT VOLTAGE RANGE
V
CM
Common-mode voltage range
(V+)
V
INPUT BIAS CURRENT
I
B
I
OS
C
LOAD
OUTPUT
I
O
≤
4 mA, input overdrive = 100 mV,
V
S
= 36 V
I
O
= 0 mA, input overdrive = 100 mV,
V
S
= 36 V
T
A
= 25°C
V
IN+
> V
IN– ,
T
J
= 25°C
2.2
I
O
= 0 A , T
A
= 25°C
I
O
= 0 A, T
A
= –55°C to 125°C
55
20
70
1100
700
mV
mV
mA
nA
Input bias current
Input offset current
Capacitive load drive
5
15
20
nA
nA
nA
V
O
Voltage output swing from rail
I
SC
Short circuit sink current
Output leakage current
POWER SUPPLY
V
S
I
Q
Specified voltage range
Quiescent current (per channel)
36
75
100
V
μA
μA
6.6 Switching Characteristics
at T
A
= –55°C to 125°C, V
S
= 2.2 V to 36 V, C
L
= 15 pF, R
PULLUP
= 5.1 kΩ, V
CM
= V
S
/ 2, and V
S
= V
PULLUP
(unless otherwise
noted)
PARAMETER
t
pHL
t
pLH
t
R
t
F
Propagation delay time, high-to-low
Propagation delay time, low-to-high
Rise time
Fall time
TEST CONDITIONS
Input overdrive = 100 mV, T
A
=
25°C
Input overdrive = 100 mV, T
A
=
25°C
Input overdrive = 100 mV, T
A
=
25°C
Input overdrive = 100 mV, T
A
=
25°C
MIN
TYP
460
560
365
240
MAX
UNIT
ns
ns
ns
ns
Copyright © 2018, Texas Instruments Incorporated
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