62A
CYM9260
CYM9261B
CYM9262A
CYM9263
64K x 72 SRAM Module
128K x 72 SRAM Module
256K x 72 SRAM Module
512K x 72 SRAM Module
Features
• Operates at 66 MHz
• Uses 64K x 18, 128K x 18, or 256K x 18 high performance
synchronous SRAMs
• 168-position Angled DIMM from Amp p/n 179508-2
• 3.3V inputs/data outputs
surface mount packages on an epoxy laminate board with
pins. The modules are designed to be incorporated into large
memory arrays.
The module is configured as either one or two banks, where
each bank has separate chip select and output enable con-
trols. Separate clocks are provided for every pair of SRAMs’s.
Multiple ground pins and on-board decoupling capacitors en-
sure high performance with maximum noise immunity.
All components on the cache modules are surface mounted on
a multi-layer epoxy laminate (FR-4) substrate. The contact
pins are plated with 150 micro-inches of nickel covered by 30
micro-inches of gold flash.
Functional Description
The CYM9260, CYM9261, CYM9262, and the CYM9263 are
high-performance synchronous memory modules organized
as 64K(9260), 128K(9261), 256K(9262), or 512K(9263) by 72
bits. These modules are constructed from either 128K x
18(9260,9261B,9262A) or 256K x 18 (9263) SRAMs in plastic
Logic Block Diagram- CYM9260
V
cc3
A[15:0]
WE[7:0]
ADSP
OE[0:1]
OE0
CS[0:1]
CS0
R3
A
15:0
ADSP
OE
CS
WEH
R1
WEL
ADSC
BANK 0
CLK[0:3]
CLK
CLK[0]
CLK[1]
CLK[2]
CLK[3]
V
cc3
R2
DQ[0:15]
DQP[0:1]
(4) 64K x 18 SRAM
R4
D[0:63]
DP[0:7]
R1, R2, R3, R4 are optional resistors
R1, R2, R4 are mounted for access using ADSC
R3, R2, R4 are mounted for access using ADSP
64Kx72
PD
1
GND
PD
0
NC
BANK 0
Cypress Semiconductor Corporation
Document #: 38-05002 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised March 27, 2002
CYM9260
CYM9261B
CYM9262A
CYM9263
Logic Block Diagram- CYM9261B/CYM9262A
V
cc3
V
cc3
A[17:0]
WE[0:7]
ADSP
OE[0:1]
OE0
CS[0:1]
CE0
R3
A
17:0
ADSP
OE
CS
WEH
WEL
CLK[0]
CLK[1]
CLK[2]
CLK[3]
R4
R2
(4) 128K x 18 SRAM
DQ[0:15]
DQP[0:1]
D[0:63]
DP[0:7]
R1
CLK[0:3]
ADSC
BANK 0
CLK
A
17:0
ADSP
R1, R2, R3, R4 are optional resistors
R1, R2, R4 are mounted for access using ADSC
R3, R2, R4 are mounted for access using ADSP
OE1
CE1
OE
CS
WEH
PD
1
NC
GND
PD
0
GND
GND
WEL
BANK 0
BANK 0 & 1
ADSC
D[0:15]
DQ[0:1]
128Kx72
256KX72
CLK
CLK[0]
CLK[1]
CLK[2]
CLK[3]
BANK 1
Document #: 38-05002 Rev. **
(4) 128K x 18 SRAM
Page 2 of 12
CYM9260
CYM9261B
CYM9262A
CYM9263
Logic Block Diagram- CYM9263
V
cc3
A[17:0]
WE[0:7]
ADSP
OE[0:1]
OE0
CS[0:1]
CE0
R3
A
17:0
ADSP
OE
CS
WEH
WEL
CLK[0]
CLK[1]
CLK[2]
CLK[3]
V
cc3
R2
(4) 256K x 18 SRAM
R4
DQ[0:15]
DQP[0:1]
D[0:63]
DP[0:7]
R1
CLK[0:3]
ADSC
BANK 0
CLK
A
17:0
R1, R2, R3, R4 are optional resistors
R1, R2, R4 are mounted for access using ADSC
R3, R2, R4 are mounted for access using ADSP
ADSP
OE1
CE1
OE
CS
WEH
WEL
PD
1
512KX72
NC
D[0:15]
DQ[0:1]
CLK[0]
CLK[1]
CLK[2]
PD
0
NC
BANK 0 & 1
ADSC
BANK 1
CLK
CLK[3]
Selection Guide
Synchronous Cache Module
Part Number
Cache Size
SRAMs Used
System Clock (MHz)
Data t
CDV
CYM9260-66
64 K x 72
4 of 64K x 18
66
10.3 ns
CYM9261B-66
128 K x 72
4 of 128K x 18
66
10.3 ns
CYM9262A-66
256 K x 72
8 of 128K x 18
66
10.3 ns
CYM9263-66
512 K x 72
8 of 256K x 18
66
10.3 ns
Document #: 38-05002 Rev. **
(4) 256K x 18 SRAM
Page 3 of 12
CYM9260
CYM9261B
CYM9262A
CYM9263
Pin Definitions
Signal
V
CC3
GND
A[17:0]
OE[1:0]
WE[7:0]
CS[1:0]
PD
0
–PD
1
D[63:0]
DP[7:0]
CLK[0:3]
ADSP
NC
RSVD
3V Supply
Ground
Addresses From Processor
Output Enables For The Two Banks
Byte Write Enables
Chip Select For The Two Banks
Presence Detect Output Pins
Data Lines From Processor
Data Parity Lines From Processor
Clock Lines To The Module
Address Strobe From The Processor
Signal Not Connected On Module
Reserved
Description
Presence Detect Pins
PD
1
CYM9260 - 64K x 72
CYM9261 - 128K x 72
CYM9262 - 256K x 72
CYM9263 - 512K x 72
GND
NC
GND
NC
PD
0
NC
GND
GND
NC
Document #: 38-05002 Rev. **
Page 5 of 12
模拟与混合信号
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