IDT74FCT841AT/CT
FAST CMOS BUS INTERFACE LATCH
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS BUS
INTERFACE LATCH
IDT74FCT841AT/CT
FEATURES:
•
•
•
•
•
•
•
•
A and C grades
Low input and output leakage
≤
1µA (max.)
CMOS power levels
True TTL input and output compatibility:
– V
OH
= 3.3V (typ.)
– V
OL
= 0.3V (typ.)
High Drive outputs (-15mA I
OH
, 48mA I
OL
)
Meets or exceeds JEDEC standard 18 specifications
Power off disable outputs permit "live insertion"
Available in SOIC, SSOP, and QSOP packages
DESCRIPTION:
The FCT841T series is built using an advanced dual metal CMOS
technology.
The FCT841T bus interface latches are designed to eliminate the extra
packages required to buffer existing latches and provide extra data width
for wider address/data paths or buses carrying parity. The FCT841T are
buffered, 10-bit wide versions of the popular FCT373T function. They are
ideal for use as an output port requiring high I
OL
/I
OH
.
All of the FCT841T high-performance interface family can drive large
capacitive loads, while providing low-capacitance bus loading at both inputs
and outputs. All inputs have clamp diodes to ground and all outputs are
designed for low-capacitance bus loading in high-impedance state.
FUNCTIONAL BLOCK DIAGRAM
D
0
D
1
D
2
D
3
D
4
D
5
D
8
D
9
D
LE Q
D
LE Q
D
LE
Q
D
LE Q
D
LE
Q
D
LE Q
D
LE
Q
D
LE
Q
LE
OE
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
8
Y
9
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
1
JUNE 2002
DSC-2571/9
© 2002 Integrated Device Technology, Inc.
IDT74FCT841AT/CT
FAST CMOS BUS INTERFACE LATCH
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
OE
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
Y
9
LE
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
(2)
V
TERM
(3)
T
STG
I
OUT
Description
Terminal Voltage with Respect to GND
Terminal Voltage with Respect to GND
Storage Temperature
DC Output Current
Max
–0.5 to +7
–0.5 to V
CC
+0.5
–65 to +150
–60 to +120
Unit
V
V
°C
mA
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability. No terminal voltage may exceed
Vcc by +0.5V unless otherwise noted.
2. Inputs and Vcc terminals only.
3. Output and I/O terminals only.
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
6
8
Max.
10
12
Unit
pF
pF
NOTE:
1. This parameter is measured at characterization but not tested.
SOIC/ SSOP/ QSOP
TOP VIEW
PIN DESCRIPTION
Pin Names
Dx
LE
I/O
I
I
Description
Latch Data Inputs
Latch Enable Input. The latches are transparent when
LE is HIGH. Input data is latched on the HIGH-to-
LOW transition.
3-State Latch Outputs
Output Enable Control. When
OE
is LOW, the
outputs are enabled. When
OE
is HIGH, the outputs
Yx are in high-impedance (off) state.
FUNCTION TABLE
(1)
OE
H
H
H
L
L
L
Inputs
LE
H
H
L
H
H
L
Dx
L
H
X
L
H
X
Internal
Qx
L
H
NC
L
H
NC
Output
Yx
Z
Z
Z
L
H
NC
Function
High Z
High Z
Latched (High Z)
Transparent
Transparent
Latched
Yx
OE
O
I
NOTE:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
Z = High Impedance
NC = No Change
2
IDT74FCT841AT/CT
FAST CMOS BUS INTERFACE LATCH
INDUSTRIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Industrial: T
A
= –40°C to +85°C, V
CC
= 5.0V ±5%
Symbol
V
IH
V
IL
I
IH
I
IL
I
OZH
I
OZL
I
I
V
IK
V
H
I
CC
Input HIGH Current
(4)
Clamp Diode Voltage
Input Hysteresis
Quiescent Power Supply Current
V
CC
= Max.
V
IN
= GND or V
CC
V
CC
= Max., V
I
= V
CC
(Max.)
V
CC
= Min., I
IN
= –18mA
—
Parameter
Input HIGH Level
Input LOW Level
Input HIGH Current
(4)
Input LOW Current
(4)
High Impedance Output Current
(4)
Test Conditions
(1)
Guaranteed Logic HIGH Level
Guaranteed Logic LOW Level
V
CC
= Max.
V
CC
= Max.
V
CC
= Max., V
I
= V
CC
(Max.)
V
I
= 2.7V
V
I
= 0.5V
V
I
= 2.7V
V
I
= 0.5V
Min.
2
—
—
—
—
—
—
—
—
—
Typ.
(2)
—
—
—
—
—
—
—
–0.7
200
0.01
Max.
—
0.8
±1
±1
±1
±1
±1
–1.2
—
1
µA
V
mV
mA
Unit
V
V
µA
µA
µA
OUTPUT DRIVE CHARACTERISTICS
Symbol
V
OH
V
OL
I
OS
I
OFF
Parameter
Output HIGH Voltage
Output LOW Voltage
Short Circuit Current
Input/Output Power Off Leakage
(5)
V
CC
= Min
V
IN
= V
IH
or V
IL
V
CC
= Min
V
IN
= V
IH
or V
IL
V
CC
= Max., V
O
= GND
(3)
Test Conditions
(1)
I
OH
= –8mA
I
OH
= –15mA
I
OL
= 48mA
Min.
2.4
2
—
–60
—
Typ.
(2)
3.3
3
0.3
–120
—
Max.
—
—
0.5
–225
±1
Unit
V
V
mA
µA
V
CC
= 0V, V
IN
or V
O
≤
4.5V
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Not more than one output should be tested at one time. Duration of the test should not exceed one second.
4. The test limit for this parameter is ±5µA at T
A
= –55°C.
5. This parameter is guaranteed but not tested.
3
IDT74FCT841AT/CT
FAST CMOS BUS INTERFACE LATCH
INDUSTRIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
Symbol
∆I
CC
I
CCD
Parameter
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
Current
(4)
V
CC
= Max.
V
IN
= 3.4V
(3)
V
CC
= Max.
Outputs Open
OE
= GND
LE = V
CC
One Input Toggling
50% Duty Cycle
V
CC
= Max.
Outputs Open
fi = 10MHz
50% Duty Cycle
OE
= GND
LE = V
CC
One Bit Toggling
V
CC
= Max.
Outputs Open
fi = 2.5MHz
50% Duty Cycle
OE
= GND
LE = V
CC
Eight Bits Toggling
V
IN
= V
CC
V
IN
= GND
Test Conditions
(1)
Min.
—
—
Typ.
(2)
0.5
0.15
Max.
2
0.25
Unit
mA
mA/
MHz
I
C
Total Power Supply Current
(6)
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
—
1.5
3.5
mA
—
1.8
4.5
V
IN
= V
CC
V
IN
= GND
V
IN
= 3.4V
V
IN
= GND
—
3
6
(5)
mA
—
5
14
(5)
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
CC
= 5.0V, +25°C ambient.
3. Per TTL driven input (V
IN
= 3.4V). All other inputs at V
CC
or GND.
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of
∆I
CC
formula. These limits are guaranteed but not tested.
6. I
C
= I
QUIESCENT
+ I
INPUTS
+ I
DYNAMIC
I
C
= I
CC
+
∆I
CC
D
H
N
T
+ I
CCD
(fiNi)
I
CC
= Quiescent Current
∆I
CC
= Power Supply Current for a TTL High Input (V
IN
= 3.4V)
D
H
= Duty Cycle for TTL Inputs High
N
T
= Number of TTL Inputs at D
H
I
CCD
= Dynamic Current caused by an Input Transition Pair (HLH or LHL)
fi = Output Frequency
Ni = Number of Outputs at fi
All currents are in milliamps and all frequencies are in megahertz.
4
IDT74FCT841AT/CT
FAST CMOS BUS INTERFACE LATCH
INDUSTRIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
74FCT841AT
Symbol
t
PLH
t
PHL
Parameter
Propagation Delay
Dx to Yx (LE = HIGH)
Condition
C
L
= 50pF
R
L
= 500Ω
(1)
Min.
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.5
2.5
4
(2)
Max.
9
13
12
16
11.5
23
7
18
—
—
—
74FCT841CT
Min.
(2)
Max.
1.5
5.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.5
2.5
4
13
6.4
15
6.5
12
5.7
6
—
—
—
Unit
ns
t
PLH
t
PHL
Propagation Delay
LE to Yx
t
PZH
t
PZL
Output Enable Time,
OE
to Yx
t
PHZ
t
PLZ
Output Disable Time,
OE
to Yx
t
SU
t
H
t
W
Data to LE Set-up Time
Data to LE Hold Time
LE Pulse Width HIGH
(3)
C
L
= 300pF
(4)
R
L
= 500Ω
C
L
= 50pF
R
L
= 500Ω
C
L
= 300pF
(4)
R
L
= 500Ω
C
L
= 50pF
R
L
= 500Ω
C
L
= 300pF
(4)
R
L
= 500Ω
C
L
= 5pF
(4)
R
L
= 500Ω
C
L
= 50pF
R
L
= 500Ω
C
L
= 50pF
R
L
= 500Ω
ns
ns
ns
ns
ns
ns
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed but not tested.
4. This condition is guaranteed but not tested.
5
无线连接
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
