CY7C138AV CY7C139AV CY7C144AV CY7C145AV CY7C006AV CY7C016AV CY7C007AV CY7C017AV 3.3V 4K/8K/16K/32K x 8/9
Dual-Port Static RAM
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
3.3V 4K/8K/16K/32K x 8/9
Dual-Port Static RAM
Features
• True Dual-Ported memory cells which allow
simultaneous access of the same memory location
• 4K/8K/16K/32K x 8 organizations
(CY7C0138AV/144AV/006AV/007AV)
• 4K/8K/16K/32K x 9 organizations
(CY7C0139AV/145AV/016AV/017AV)
• 0.35-micron CMOS for optimum speed/power
• High-speed access: 20/25 ns
• Low operating power
— Active: I
CC
= 115 mA (typical)
— Standby: I
SB3
= 10
µA
(typical)
• Fully asynchronous operation
• Automatic power-down
• Expandable data bus to 16/18 bits or more using Master/
Slave chip select when using more than one device
• On-chip arbitration logic
• Semaphores included to permit software handshaking
between ports
• INT flag for port-to-port communication
• Pin select for Master or Slave
• Commercial and Industrial Temperature Ranges
• Available in 68-pin PLCC (all) and 64-pin TQFP
(7C006AV & 7C144AV)
• Pb-Free packages available
Logic Block Diagram
R/W
L
CE
L
OE
L
R/W
R
CE
R
OE
R
I/O
0L
–I/O
7/8L
[1]
8/9
8/9
[1]
I/O
Control
I/O
Control
I/O
0R
–I/O
7/8R
A
0L
–A
11–14L
[2]
12–15
Address
Decode
12–15
True Dual-Ported
RAM Array
Address
Decode
12–15
12–15
A
0R
–A
11–14R
[2]
[2]
A
0L
–A
11–14L
CE
L
OE
L
R/W
L
SEM
L
BUSY
L
INT
L
Interrupt
Semaphore
Arbitration
[3]
A
0R
–A
11–14R
CE
R
OE
R
R/W
R
SEM
R
[3]
[2]
BUSY
R
INT
R
M/S
For the most recent information, visit the Cypress web site at www.cypress.com
Notes:
1. I/O
0
–I/O
7
for x8 devices; I/O
0
–I/O
8
for x9 devices.
2. A
0
–A
11
for 4K devices; A
0
–A
12
for 8K devices; A
0
–A
13
for 16K devices; A
0
–A
14
for 32K devices;
3. BUSY is an output in master mode and an input in slave mode.
Cypress Semiconductor Corporation
Document #: 38-06051 Rev. *C
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised June 6, 2005
CY7C138AV/144AV/006AV
CY7C139AV/145AV/016AV
CY7C007AV/017AV
Pin Definitions
Left Port
CE
L
R/W
L
OE
L
A
0L
–A
14L
I/O
0L
–I/O
8L
SEM
L
INT
L
BUSY
L
M/S
V
CC
GND
NC
Right Port
CE
R
R/W
R
OE
R
A
0R
–A
14R
I/O
0R
–I/O
8R
SEM
R
INT
R
BUSY
R
Chip Enable
Read/Write Enable
Output Enable
Address (A
0
–A
11
for 4K devices; A
0
–A
12
for 8K devices; A
0
–A
13
for 16K devices; A
0
–A
14
for 32K)
Data Bus Input/Output (I/O
0
–I/O
7
for x8 devices and I/O
0
–I/O
8
for x9)
Semaphore Enable
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
No Connect
or token, from one port to the other to indicate that a shared
resource is in use. The semaphore logic is comprised of eight
shared latches. Only one side can control the latch
(semaphore) at any time. Control of a semaphore indicates
that a shared resource is in use. An automatic power-down
feature is controlled independently on each port by a Chip
Select (CE) pin.
Read and Write Operations
When writing data must be set up for a duration of t
SD
before
the rising edge of R/W in order to guarantee a valid write. A
write operation is controlled by either the R/W pin (see Write
Cycle No. 1 waveform) or the CE pin (see Write Cycle No. 2
waveform). Required inputs for non-contention operations are
summarized in
Table 1.
If a location is being written to by one port and the opposite
port attempts to read that location, a port-to-port flowthrough
delay must occur before the data is read on the output;
otherwise the data read is not deterministic. Data will be valid
on the port t
DDD
after the data is presented on the other port.
When reading the device, the user must assert both the OE
and CE pins. Data will be available t
ACE
after CE or t
DOE
after
OE is asserted. If the user wishes to access a semaphore flag,
then the SEM pin must be asserted instead of the CE pin and
OE must also be asserted.
Interrupts
The upper two memory locations may be used for message
passing. The highest memory location (FFF for the
CY7C138AV/9AV, 1FFF for the CY7C144AV/5AV, 3FFF for the
CY7C006AV/16AV, 7FFF for the CY7C007AV/17AV) is the
mailbox for the right port and the second-highest memory
location (FFE for the CY7C138AV/9AV, 1FFE for the
CY7C144AV/5AV, 3FFE for the CY7C006AV/16AV, 7FFE for
the CY7C007AV/17AV) is the mailbox for the left port. When
one port writes to the other port’s mailbox, an interrupt is
generated to the owner. The interrupt is reset when the owner
reads the contents of the mailbox. The message is user
defined.
Each port can read the other port’s mailbox without resetting
the interrupt. The active state of the busy signal (to a port)
Page 5 of 20
Description
Architecture
The CY7C138AV/144AV/006AV/007AV and CY7C139AV/
145AV/016AV/017AV consist of an array of 4K, 8K, 16K, and
32K words of 8 and 9 bits each of dual-port RAM cells, I/O and
address lines, and control signals (CE, OE, R/W). These
control pins permit independent access for reads or writes to
any location in memory. To handle simultaneous writes/reads
to the same location, a BUSY pin is provided on each port. Two
interrupt (INT) pins can be utilized for port-to-port communi-
cation. Two semaphore (SEM) control pins are used for
allocating shared resources. With the M/S pin, the device can
function as a master (BUSY pins are outputs) or as a slave
(BUSY pins are inputs). The device also has an automatic
power-down feature controlled by CE. Each port is provided
with its own output enable control (OE), which allows data to
be read from the device.
Functional Description
The CY7C138AV/144AV/006AV/007AV and CY7C139AV/
145AV/ 016AV/017AV are low-power CMOS 4K, 8K, 16K, and
32K x8/9 dual-port static RAMs. Various arbitration schemes
are included on the devices to handle situations when multiple
processors access the same piece of data. Two ports are
provided, permitting independent, asynchronous access for
reads and writes to any location in memory. The devices can
be utilized as standalone 8/9-bit dual-port static RAMs or
multiple devices can be combined in order to function as a
16/18-bit or wider master/slave dual-port static RAM. An M/S
pin is provided for implementing 16/18-bit or wider memory
applications without the need for separate master and slave
devices or additional discrete logic. Application areas include
interprocessor/multiprocessor designs, communications
status buffering, and dual-port video/graphics memory.
Each port has independent control pins: Chip Enable (CE),
Read or Write Enable (R/W), and Output Enable (OE). Two
flags are provided on each port (BUSY and INT). BUSY
signals that the port is trying to access the same location
currently being accessed by the other port. The Interrupt flag
(INT) permits communication between ports or systems by
means of a mail box. The semaphores are used to pass a flag,
Document #: 38-06051 Rev. *C
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