notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the
latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc.
– www.issi.com –
Rev. 00A, 11/17/2009
1
IS43DR86400, IS43/46DR16320
Package Ball‐out and Description
DDR2 SDRAM (64Mx8) BGA Ball‐out (Top‐View) (10.00 mm X 10.50 mm Body, 0.8 mm pitch)
1 2 3 4 5 6 7 8 9
A
B
C
D
E
F
G
H
J
K
L
VDD
RDQS
VSS
DQ6
VSSQ
DM/RDQS
VSSQ
DQS
VDDQ
DQS
VSSQ DQ7
VDDQ DQ1 VDDQ
DQ4
VSSQ DQ3
VSS
WE
BA1
A1
A5
A9
NC
VDDQ DQ0 VDDQ
DQ2
VSSQ DQ5
VDDL VREF
CKE
NC
BA0
A10
VSS
A3
A7
VDD
A12
VSSDL
LDQS
VDD
RAS
CAS
A2
A6
A11
NC
CK
CS
A0
A4
A8
A13
VSS
VDD
ODT
Not populated
Symbol
CK, CK#
CKE
CS#
RAS#,CAS#,WE#
Ax
BAx
DQx
DQS, DQS#
RDQS, RDQS#
DM
VDD
VSS
VDDQ
VSSQ
VREF
VDDL
VSSDL
ODT
NC
Description
Input clocks
Clock enable
Chip Select
Command control pins
Address
Bank Address
I/O
Data Strobe
Redundant Data Strobe
Input data mask
Supply voltage
Ground
DQ power supply
DQ ground
Reference voltage
DLL power supply
DLL ground
On Die Termination Enable
No connect
Notes:
1. Pins B3 and A2 have identical capacitance as pins B7
and A8.
2. For a read, when enabled, strobe pair RDQS & RDQS#
are identical in function and timing to strobe pair DQS &
DQS# and input masking function is disabled.
3. The function of DM or RDQS/RDQS# are enabled by
EMRS command.
4. VDDL and VSSDL are power and ground for the DLL. It
is recommended that they are isolated on the device
from VDD, VDDQ, VSS, and VSSQ.
Integrated Silicon Solution, Inc.
– www.issi.com –
Rev. 00A, 11/17/2009
2
IS43DR86400, IS43/46DR16320
DDR2 SDRAM (32Mx16) BGA Ball‐out (Top‐View) (10.50 mm X 13.00 mm Body, 0.8 mm pitch)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
2
3
4
5
6
7
8
9
VDD
NC
VSS
VSSQ
UDQS
VDDQ
UDQS VSSQ DQ15
VDDQ DQ8 VDDQ
DQ10 VSSQ DQ13
VSSQ
LDQS
VDDQ
LDQS VSSQ DQ7
VDDQ DQ0 VDDQ
DQ2
VSSDL
RAS
CAS
A2
A6
A11
NC
VSSQ DQ5
CK
CK
CS
A0
A4
A8
NC
VSS
VDD
VDD
ODT
DQ14 VSSQ UDM
VDDQ DQ9 VDDQ
DQ12 VSSQ DQ11
VDD
DQ6
NC
VSS
VSSQ LDM
VDDQ DQ1 VDDQ
DQ4
VSSQ
DQ3
VSS
WE
BA1
VDDL VREF
CKE
NC
BA0
A10/AP A1
VSS
A3
A7
VDD
A12
A5
A9
NC
Not populated
Symbol
CK, CK#
CKE
CS#
RAS#,CAS#,WE#
Ax
BAx
DQx
UDQS, UDQS#
LDQS, LDQS#
UDM, LDM
VDD
VSS
VDDQ
VSSQ
VREF
VDDL
VSSDL
ODT
NC
Description
Input clocks
Clock enable
Chip Select
Command control inputs
Address
Bank Address
I/O
Upper Byte Data Strobe
Lower Byte Data Strobe
Input data mask
Supply voltage
Ground
DQ power supply
DQ ground
Reference voltage
DLL power supply
DLL ground
On Die Termination Enable
No connect
Note:
VDDL and VSSDL are power and ground for the DLL. It is
recommended that they are isolated on the device from
VDD, VDDQ, VSS, and VSSQ.
Integrated Silicon Solution, Inc.
– www.issi.com –
Rev. 00A, 11/17/2009
3
IS43DR86400, IS43/46DR16320
Functional Description
Power‐up and Initialization
DDR2 SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may
result in undefined operation.
Power‐up and Initialization Sequence
The following sequence is required for Power‐up and Initialization.
1. Either one of the following sequence is required for Power‐up:
A. While applying power, attempt to maintain CKE below 0.2 x VDDQ and ODT* at a LOW state (all other inputs may be
undefined.) The VDD voltage ramp time must be no greater than 200 ms from when VDD ramps from 300 mV to
VDD(Min); and during the VDD voltage ramp, |VDD‐VDDQ|
≥
0.3 V. Once the ramping of the supply voltages is
complete (when VDDQ crosses VDDQ(Min)), the supply voltage specifications provided in the table Recommended DC
Operating Conditions (SSTL_1.8), prevail.
−
VDD, VDDL and VDDQ are driven from a single power converter output, AND
−
VTT is limited to 0.95V max, AND
−
VREF tracks VDDQ/2, VREF must be within ± 300mV with respect to VDDQ/2 during supply ramp time.
−
VDDQ ≥ VREF must be met at all times
B. While applying power, attempt to maintain CKE below 0.2 x VDDQ and ODT* at a LOW state (all other inputs may be
undefined, voltage levels at I/Os and outputs must be less than VDDQ during voltage ramp time to avoid DRAM latch‐
up. During the ramping of the supply voltages, VDD ≥ VDDL ≥ VDDQ must be maintained and is applicable to both AC
and DC levels until the ramping of the supply voltages is complete, which is when VDDQ crosses VDDQ min. Once the
ramping of the supply voltages is complete, the supply voltage specifications provided in the table Recommended DC
Operating Conditions (SSTL‐1.8), prevail.
−
Apply VDD/VDDL before or at the same time as VDDQ.
−
VDD/VDDL voltage ramp time must be no greater 200 ms from when VDD ramps from 300 mV to VDD(Min) .
−
Apply VDDQ before or at the same time as VTT.
−
The VDDQ voltage ramp time from when VDD(Min) is achieved on VDD to the VDDQ(Min) is achieved on VDDQ
must be no greater than 500 ms.
2. Start clock and maintain stable condition.
3. For the minimum of 200 µs after stable power (VDD, VDDL, VDDQ, VREF, and VTT values are in the range of the minimum and
maximum values specified in the table Recommended DC Operating Conditions (SSTL‐1.8)) and stable clock (CK, CK#), then apply
NOP or Deselect and assert a logic HIGH to CKE.
4. Wait minimum of 400 ns then issue a precharge all command. During the 400 ns period, a NOP or Deselect command must be
issued to the DRAM.
5. Issue an EMRS command to EMR(2).
6. Issue an EMRS command to EMR(3).
7. Issue EMRS to enable DLL.
8. Issue a Mode Register Set command for DLL reset.
9. Issue a precharge all command.
10. Issue 2 or more auto‐refresh commands.
11. Issue a MRS command with LOW to A8 to initialize device operation. (i.e. to program operating parameters without resetting
the DLL.)
12. Wait at least 200 clock cycles after step 8 and then execute OCD Calibration (Off Chip Driver impedance adjustment). If OCD
calibration is not used, EMRS Default command (A9=A8=A7=HIGH) followed by EMRS OCD Calibration Mode Exit command
(A9=A8=A7=LOW) must be issued with other operating parameters of EMR(1).
13. The DDR2 SDRAM is now ready for normal operation.
Note*: To guarantee ODT off, VREF must be valid and a LOW level must be applied to the ODT pin.
Integrated Silicon Solution, Inc.
– www.issi.com –
Rev. 00A, 11/17/2009
4
IS43DR86400, IS43/46DR16320
Initialization Sequence after Power‐Up Diagram
tCH
tCL
CK
tIS
~
~
~
NOP
~
~
~
PRE
ALL
~
~
~
EMRS
~
~
~
MRS
~
~
~
PRE
ALL
~
~
~
REF
~
~
~
~
tRFC
REF
~
~
~
~
tRFC
MRS
~
~
~
~
tMRD
EMRS
~
~
~
~
Follow OCD
Flowchart
EMRS
~
~
tIS
CK#
ODT
~
~
tOIT
Any
Com
Command
~
400ns
~
tRP
~
tMRD
~
tMRD
~
tRP
~
Minimum 200 Cycles
DLL
Enable
DLL
Reset
OCD
Default
OCD Cal.
Mode Exit
Programming the Mode Register and Extended Mode Registers
For application flexibility, burst length, burst type, CAS# latency, DLL reset function, write recovery time (WR) are user defined
variables and must be programmed with a Mode Register Set (MRS) command. Additionally, DLL disable function, driver impedance,
additive CAS latency, ODT (On Die Termination), single‐ended strobe, and OCD (off chip driver impedance adjustment) are also user
defined variables and must be programmed with an Extended Mode Register Set (EMRS) command. Contents of the Mode Register
(MR) or Extended Mode Registers EMR[1] and EMR[2] can be altered by re‐executing the MRS or EMRS Commands. Even if the user
chooses to modify only a subset of the MR, EMR[1], or EMR[2] variables, all variables within the addressed register must be
redefined when the MRS or EMRS commands are issued. The x16 option does not have A13, so all references to this address can be
ignored for this option.
MRS, EMRS and Reset DLL do not affect memory array contents, which mean re‐initialization including those can be executed at any
time after power‐up without affecting memory array contents.
DDR2 Mode Register (MR) Setting
The mode register stores the data for controlling the various operating modes of DDR2 SDRAM. It controls CAS# latency, burst
length, burst sequence, DLL reset, tWR, and active power down exit time to make DDR2 SDRAM useful for various applications. The
default value of the mode register is not defined, therefore the mode register must be written after power‐up for proper operation.
The mode register is written by asserting LOW on CS#, RAS#, CAS#, WE#, BA0 and BA1, while controlling the state of address pins A0
– A13. The DDR2 SDRAM should be in all bank precharge with CKE already HIGH prior to writing into the mode register. The mode
register set command cycle time (tMRD) is required to complete the write operation to the mode register. The mode register
contents can be changed using the same command and clock cycle requirements during normal operation as long as all banks are in
the precharge state. The mode register is divided into various fields depending on functionality. Burst length is defined by A0 ‐ A2
with options of 4 and 8 bit burst lengths. The burst length decodes are compatible with DDR SDRAM. Burst address sequence type is
defined by A3; CAS latency is defined by A4 ‐ A6. The DDR2 doesn’t support half clock latency mode. A7 is used for test mode. A8 is
used for DLL reset. A7 must be set to LOW for normal MRS operation. Write recovery time tWR is defined by A9 ‐ A11. Refer to the
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