IDTCV115-2
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PROGRAMMABLE FLEXPC™
CLOCK FOR P4 PROCESSOR
IDTCV115-2
FEATURES:
One high precision N Programming PLL for CPU
One high precision N Programming PLL for SRC/PCI
One high precision PLL for SATA
One high precision PLL for 96MHz/48MHz
Band-gap circuit for differential outputs
Support multiple spread spectrum modulation, down and
center
• Support SMBus block read/write, index read/write
• Selectable output strength for REF, PCI, and 48MHz
• Available in SSOP package
•
•
•
•
•
•
DESCRIPTION:
IDTCV115-2 is a 56 pin clock device, complying the latest Intel CK410
requirements, for Intel advance P4 processors. The CPU output buffer is
designed to support up to 400MHz processor. One dedicated PLL for Serial
ATA clock provides high accuracy frequency. This device also implements
Band-gap referenced I
REF
to reduce the impact of V
DD
variation on differential
outputs, which can provide more robust system performance.
Each CPU/SRC/PCI, SATA clock has its own Spread Spectrum selection,
which allows for isolated changes instead of affecting other clock groups.
KEY SPECIFICATION:
•
•
•
•
CPU/SRC CLK cycle to cycle jitter < 85ps
SATA CLK cycle to cycle jitter < 85ps
Static PLL frequency divide error < 114 ppm
Static PLL frequency divide error for 48MHz < 5 ppm
FUNCTIONAL BLOCK DIAGRAM
SATA PLL
SCC
SATA/
SRC4 - SATA
PCI[4:0], PCIF[2:0]
PCI/
14.318MHz
Osc
PCIEX PLL
SCC
N Programming
PCIE/
SRC[6:5] [3:1]
MUX
CPU PLL
SCC
N Programming
CPU_ITP/
SRC7
Host/
CPU[1:0]
48MHz/
USB48
Fixed PLL
No SCC
DOT96
96MHz/
RESET
OUTPUT TABLE
CPU
2
CPU_ITP/SRC
1
SRC
5
SATA
1
PCI/PCIF
8
REF/PCI
1
REF
1
DOT96
1
24_48MHz
1
RESET
1
TURBO
2
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
© 2004 Integrated Device Technology, Inc.
APRIL 2004
DSC 6544/9
IDTCV115-2
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
V
DD
_PCI
V
SS
_PCI
PCI2
PCI3
(1)
TEST MODE SELECT
(1)
If TEST_SEL sampled above 2V at V
TT
_P
WRGD
active LOW
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PCI1
PCI0
FS_A(REF1/PCI5)
(3)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
V
DD
_suspend
FS_C/REF0
Pin38
(test_mode)
1
0
CPU
REF/N
Hi-Z
SRC
REF/N
Hi-Z
PCI/F
REF/N
Hi-Z
REF
REF
Hi-Z
DOT96
REF/N
Hi-Z
USB
REF/N
Hi-Z
PCI4/Turbo1
V
SS
_PCI
V
DD
_PCI
PCIF0/ITP_EN
PCIF1
PCIF2
V
SS
_REF
XTAL_IN
XTAL_OUT
NOTE:
1. Once test clock operation has been invoked, TEST_MODE pin will select between
the Hi-Z and REF/N,
V
DD
_REF
SCL
(2)
SDA
(2)
V
DD_
48
FS_B/USB48MHz
CPUT0
CPUC0
ITP_EN
ITP_EN
1
0
pin 35
CPUC2_ITP
SRCC7
pin 36
CPUT_ITP
SRCT7
V
SS_
48
DOT_96
DOT_96#
(2)
V
DD
_CPU
CPUT1
CPUC1
V
TT
_P
WRGD
/
P
WRDWN#
SRCT1
SRCC1
V
SS
_CPU
I
REF
Reset#
Turbo2
(4)
V
DD
_SRC
V
SS
SRCT2
SRCC2
SRCT3
SRCC3
CPU2_ITP/SRCT7
CPU2_ITP/SRCC7
V
DD
_SRC
SRCT6
SRCC6
SRCT5
SRCC5
V
SS_
GND
SRCT4_SATA
SRCC4_SATA
V
DD
_SRC
V
SS
_SRC
NOTES:
1. After power on, pin 5 is tristate (see Byte 30 and Byte 2).
2. ~ 130KΩ internal pull-up.
3. After power on, REF1/PCI5 is tristate (see Byte 1).
4. Disabled at power on.
SSOP
TOP VIEW
HW FREQUENCY SELECTION TABLE
FSC, B, A
101
001
011
010
000
100
110
111
CPU
100
133
166
200
266
333
400
Reserve
SRC4_SATA
100
100
100
100
100
100
100
100
SRC[3:1], SCR[7:5]
100
100
100
100
100
100
100
100
2
PCI
33.3
33.3
33.3
33.3
33.3
33.3
33.3
33.3
USB
48
48
48
48
48
48
48
48
DOT
96
96
96
96
96
96
96
96
REF
14.318
14.318
14.318
14.318
14.318
14.318
14.318
14.318
IDTCV115-2
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
V
DD
_PCI
V
SS
_PCI
PCI2
PCI3
PCI4/Turbo1
V
SS
_PCI
V
DD
_PCI
PCIF0/ITP_EN
PCIF1
PCIF2
V
DD
_48
FS_B/USB48
V
SS
_48
DOT_96T
DOT_96C
V
TT
_P
WRGD
/P
WRDWN
#
Type
PWR
GND
OUT
OUT
OUT
GND
PWR
I/0
OUT
OUT
PWR
I/O
GND
OUT
OUT
I/O
Description
3.3V
GND
PCI clock
PCI clock
PCI clock output or Turbo input. Byte 30, bit 3 mode selection. Byte 30, bit 3 = 1, PCI clock. 0 = Turbo
mode. In Turbo mode, 1 = load TCN and TPN into CPU and SRC PLL.
GND
3.3V
PCI clock, free running. CPU_2 select (sampled at V
TT
_P
WRGD
assertion), HIGH = CPU_2.
PCI clock,
PCI clock,
3.3V
CPU Frequency selection. 48MHz afterward.
GND
96MHz 0.7V current mode differential clock output
96MHz 0.7V current mode differential clock output
3.3V LVTTL input is a level-sensitive strobe used to latch the FS_A, FS_B, FS_C/TEST_SEL and
PCIF_0/ITP_EN inputs. After V
TT
_P
WRGD
assertion, active HIGH, becomes a real-time input for
asserting power down (active LOW). Internal pull HIGH.
Differential Serial reference clock
Differential Serial reference clock
3.3V
GND
Differential Serial reference clock
Differential Serial reference clock
Differential Serial reference clock
Differential Serial reference clock
GND
SATA clock
SATA clock
3.3V
GND
Differential Serial reference clock
Differential Serial reference clock
Differential Serial reference clock
Differential Serial reference clock
3.3V
Selectable CPU or SRC differential clock output. ITP_EN=0 @ V
TT
_P
WRGD
assertion = SRC_7
Selectable CPU or SRC differential clock output. ITP_EN=0 @ V
TT
_P
WRGD
assertion = SRC_7
Load TCN2 into CPU PLL. Disabled at power on (see Byte 26).
Reset output
Reference current for differential output buffer
GND
Host 0.7V current mode differential clock output
Host 0.7V current mode differential clock output
3.3V
Host 0.7V current mode differential clock output
Host 0.7V current mode differential clock output
SMBus data
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
SRCT1
SRCC1
V
DD
_SRC
V
SS
SRCT2
SRCC2
SRCT3
SRCC3
V
SS
SRCT4_SATA
SRCC4_SATA
V
DD
_SRC
V
SS
_SRC
SRCC5
SRCT5
SRCC6
SRCT6
V
DD
_SRC
CPUC2_ITP/ SRCC7
CPUT2_ITP/ SRCT7
Turbo2
Reset#
IREF
V
SS
CPUC1
CPUT1
V
DD
_CPU
CPUC0
CPUT0
SDA
OUT
OUT
PWR
GND
OUT
OUT
OUT
OUT
GND
OUT
OUT
PWR
GND
OUT
OUT
OUT
OUT
PWR
OUT
OUT
IN
OUT
OUT
GND
OUT
OUT
PWR
OUT
OUT
I/O
3
IDTCV115-2
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (CONT.)
Pin Number
47
48
49
50
51
52
53
54
55
56
Name
SCL
V
DD
_REF
XTAL_OUT
XTAL_IN
V
SS
_REF
FS_C/REF0
V
DD
_Suspend
FS_A(REF1/PCI5)
PCI0
PCI1
Type
IN
PWR
OUT
IN
GND
I/O
POWER
I/O
OUT
OUT
Description
SMBus CLK
3.3V
Xtal output
Xtal input
GND
CPU frequency selection input at V
TT
_P
WRGD
assertion. 14.318 reference clock output afterward.
Keep supply 3.3V in the power down
CPU frequency selection input at V
TT
_P
WRGD
assertion. 14.318 or PCI reference clock output afterward,
SMBus selectable. Tristate at power on.
PCI clock
PCI clock
SM PROTOCOL
INDEX BLOCK WRITE PROTOCOL
Bit
1
2-9
10
11-18
19
20-27
28
29-36
37
38-45
46
# of bits
1
8
1
8
1
8
1
8
1
8
1
From
Master
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Description
Start
D2h
Ack (Acknowledge)
Register offset byte (starting byte)
Ack (Acknowledge)
Byte count, N, (0 is not valid
Ack (Acknowledge)
first data byte (Offset data byte)
Ack (Acknowledge)
2nd data byte
Ack (Acknowledge)
:
Nth data byte
Acknowledge
Stop
INDEX BLOCK READ PROTOCOL
Master can stop reading any time by issuing the stop bit without waiting
until Nth byte (byte count bit30-37).
Bit
1
2-9
10
11-18
19
20
21-28
29
30-37
38
39-46
47
48-55
# of bits
1
8
1
8
1
1
8
1
8
1
8
1
8
From
Master
Master
Slave
Master
Slave
Master
Master
Slave
Slave
Master
Slave
Master
Slave
Description
Start
D2H
Ack (Acknowledge)
Register offset byte (starting byte)
Ack (Acknowledge)
Repeated Start
D3H
Ack (Acknowledge)
Byte count, N (block read back of N
bytes), Byte 8
Ack (Acknowledge)
first data byte (Offset data byte)
Ack (Acknowledge)
2nd data byte
Ack (Acknowledge)
:
Ack (Acknowledge)
Nth data byte
Not acknowledge
Stop
Master
Slave
Master
INDEX BYTE WRITE
Setting bit[11:18] = starting address, bit[20:27] = 01h.
4
INDEX BYTE READ
Setting bit[11:18] = starting address. After reading back the first data byte,
master issues Stop bit.
IDTCV115-2
PROGRAMMABLE FLEXPC™ CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
CB1_[2:0], CB2_[2:0], CPU MODE
SELECTION
CB[2:0]
101
001
011
010
000
100
110
111
CPU Mode, MHz
100
133
166
200
266
333
400
RESERVE
RESOLUTION
CPU
CPU
CPU
CPU
CPU
CPU
CPU
SRC
= 100MHz mode
= 133MHz mode
= 166MHz mode
= 200MHz mode
= 266MHz mode
= 333MHz mode
= 400MHz mode
(PCI Express)
N Resolution (MHz)
0.666667
0.888889
1.333333
1.333333
2.666667
2.666667
2.666667
0.666667
%
0.67%
0.67%
0.8%
0.67%
1.00%
0.8%
0.67%
0.67%
N=
150
150
125
150
100
125
150
150
SSC MAGNITUDE CONTROL
SMC[2:0]
000
001
010
011
100
101
110
111
%
OFF
- 0.25
- 0.5
±0.125
±0.25
±0.375
±0.5
±0.75
PCI
When Byte5 bit6 = 0
PCIS[1:0]
00
01
10
11
PCI
33.33
36.36
40
S_CBS[1:0], H_CBS[1:0] BAND
SELECTION
CBS[1:0]
00
01
10
11
FS[C,B,A]
CB1_[2:0]
CB2_[2:0]
Don’t care
S_CNS, S_PNS, H_CNS,H_PNS N
SELECTION
NS[1:0]
00
01
10
11
Standard of Each CPU Mode (Band)
N Selection 1
N Selection 2
Don’t care
S.E. CLOCK STRENGTH SELECTION (PCI, REF, USB48)
Str[1:0]
00
01
10
11
2L
1H
1L
2H
Multiple loads
Recommend
Single loads
Recommend
Recommend
Recommend
Recommend
USB48
Recommend
5
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