RoboClock
CY7B993V
CY7B994V
High-speed Multi-phase PLL Clock Buffer
Features
• 500-ps max. Total Timing Budget™ (TTB™) window
• 12–100-MHz (CY7B993V), or 24–200-MHz (CY7B994V)
input/output operation
• Matched pair output skew < 200 ps
• Zero input-to-output delay
•
18 LVTTL outputs driving 50Ω terminated lines
• 16 outputs at 200 MHz: Commercial temperature
• 6 outputs at 200 MHz: Industrial temperature
• 3.3V LVTTL/LVPECL, fault-tolerant, and hot insertable
reference inputs
• Phase adjustments in 625-/1300-ps steps up to ± 10.4 ns
• Multiply/divide ratios of 1–6, 8, 10, 12
• Individual output bank disable
• Output high-impedance option for testing purposes
• Fully integrated phase-locked loop (PLL) with lock
indicator
• <50-ps typical cycle-to-cycle jitter
• Single 3.3V ± 10% supply
• 100-pin TQFP package
• 100-lead BGA package
Functional Description
The CY7B993V and CY7B994V High-speed Multi-phase PLL
Clock Buffers offer user-selectable control over system clock
functions. This multiple-output clock driver provides the
system integrator with functions necessary to optimize the
timing of high-performance computer and communication
systems.
These devices feature a guaranteed maximum TTB window
specifying all occurrences of output clocks with respect to the
input reference clock across variations in output frequency,
supply voltage, operating temperature, input edge rate, and
process.
Eighteen configurable outputs each drive terminated trans-
mission lines with impedances as low as 50Ω while delivering
minimal and specified output skews at LVTTL levels. The outputs
are arranged in five banks. Banks 1 to 4 of four outputs allow
a divide function of 1 to 12, while simultaneously allowing
phase adjustments in 625–1300-ps increments up to 10.4 ns.
One of the output banks also includes an independent clock
invert function. The feedback bank consists of two outputs,
which allows divide-by functionality from 1 to 12 and limited
phase adjustments. Any one of these eighteen outputs can be
connected to the feedback input as well as driving other inputs.
Selectable reference input is a fault tolerance feature that
allows smooth change-over to secondary clock source, when
the primary clock source is not in operation. The reference
inputs and feedback inputs are configurable to accommodate
both LVTTL or Differential (LVPECL) inputs. The completely
integrated PLL reduces jitter and simplifies board layout.
FBKA+
FBKA–
FBKB+
FBKB–
FBSEL
REFA+
REFA–
REFB+
REFB–
REFSEL
FBF0
FBDS0
FBDS1
FBDIS
4F0
4F1
4DS0
4DS1
DIS4
3F0
3F1
3DS0
3DS1
DIS3
INV3
2F0
2F1
2DS0
2DS1
DIS2
1F0
1F1
1DS0
1DS1
DIS1
LOCK
Phase
Freq.
Detector
Filter
VCO
Control Logic
Divide and Phase
Generator
Functional
Block Diagram
FS
OUTPUT_MODE
Divide and
Phase
Select
Matrix
Divide and
Phase
Select
Matrix
3
3
Feedback Bank
3
3
3
3
3
3
3
QFA0
QFA1
Bank 4
4QA0
4QA1
4QB0
4QB1
3QA0
3QA1
3QB0
3QB1
2QA0
2QA1
2QB0
2QB1
1QA0
1QA1
1QB0
1QB1
Bank 3
3
3
3
3
3
3
3
3
3
Divide and
Phase
Select
Matrix
Bank 2
Divide and
Phase
Select
Matrix
Bank 1
3
3
3
3
Divide and
Phase
Select
Matrix
Cypress Semiconductor Corporation
Document #: 38-07127 Rev. *F
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised August 10, 2005
RoboClock
CY7B993V
CY7B994V
Pin Configurations
100-pin TQFP
FBDS1
FBDS0
FBKB+
FBKA+
FBKB–
FBSEL
FBKA–
VCCQ
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
VCCN
VCCN
VCCN
LOCK
QFA0
QFA1
1QB1
1QB0
1QA1
1QA0
GND
GND
GND
GND
GND
GND
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
GND
3F1
4F1
3F0
4F0
4DS1
3DS1
GND
4QB1
VCCN
4QB0
GND
GND
4QA1
VCCN
4QA0
GND
2DS1
1DS1
VCCQ
4DS0
3DS0
2DS0
1DS0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VCCQ
REFA+
REFA –
REFSEL
REFB–
REFB+
2F0
FS
GND
2QA0
VCCN
2QA1
GND
GND
2QB0
VCCN
2QB1
GND
FBF0
1F0
GND
VCCQ
FBDIS
DIS4
DIS3
CY7B993/4V
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCCN
VCCN
OUTPUT_MODE
VCCQ
VCCQ
VCCQ
Document #: 38-07127 Rev. *F
VCCQ
3QA0
3QA1
3QB0
3QB1
GND
2F1
1F1
INV3
DIS1
DIS2
Page 2 of 15
RoboClock
CY7B993V
CY7B994V
Pin Configurations
(continued)
100-lead BGA
1
1QB1
2
1QB0
3
1QA1
4
1QA0
5
QFA0
6
QFA1
7
FBKB+
8
VCCQ
9
FBKA–
10
FBKA+
A
B
VCCN
VCCN
VCCN
VCCN
VCCN
VCCN
VCCQ
FBKB–
FBSEL
REFA+
C
GND
GND
GND
GND
GND
GND
VCCQ
GND
GND
REFA–
D
LOCK
4F0
3F1
(3_level) (3_level)
4DS1
(3_level)
3DS1
(3_level)
GND
FBDS1 FBDS0
2F0
(3_level) (3_level) (3_level)
3F0
4F1
(3_level) (3_level)
VCCQ
REFSEL REFB–
E
4QB1
VCCN
GND
GND
FS
(3_level)
FBF0
(3_level)
VCCN
REFB+
F
4QB0
VCCN
GND
GND
GND
GND
VCCN
2QA0
G
4QA1
2DS1
(3_level)
VCCQ
GND
GND
GND
GND
VCCQ
1F0
(3_level)
2QA1
H
4QA0
1DS1
1DS0
(3_level) (3_level)
VCCQ
GND
GND
VCCQ
OUTPUT
MODE FBDIS
(3_level)
INV3
(3_level)
DIS3
2QB0
J
4DS0
3DS0
2DS0
(3_level) (3_level) (3_level)
2F1
1F1
(3_level) (3_level)
DIS1
VCCN
VCCN
GND
2QB1
K
DIS2
VCCN
3QA0
3QA1
GND
3QB0
3QB1
DIS4
Pin Definitions
Pin Name
FBSEL
FBKA+, FBKA–
FBKB+, FBKB–
[1]
I/O
Input
Input
Pin Type
LVTTL
LVTTL/
LVDIFF
Pin Description
Feedback Input Select:
When LOW, FBKA inputs are selected. When HIGH, the FBKB
inputs are selected. This input has an internal pull-down.
Feedback Inputs:
One pair of inputs selected by the FBSEL is used to feedback the clock
output xQn to the phase detector. The PLL will operate such that the rising edges of the
reference and feedback signals are aligned in both phase and frequency. These inputs
can operate as differential PECL or single-ended TTL inputs. When operating as a
single-ended LVTTL input, the complementary input must be left open.
Reference Inputs:
These inputs can operate as differential PECL or single-ended TTL
reference inputs to the PLL. When operating as a single-ended LVTTL input, the comple-
mentary input must be left open.
Reference Select Input:
The REFSEL input controls how the reference input is
configured. When LOW, it will use the REFA pair as the reference input. When HIGH, it
will use the REFB pair as the reference input. This input has an internal pull-down.
Frequency Select:
This input must be set according to the nominal frequency (f
NOM
) (see
Table 1).
Feedback Output Phase Function Select:
This input determines the phase function of
the Feedback bank’s QFA[0:1] outputs (see
Table 3).
REFA+, REFA–
REFB+, REFB–
REFSEL
Input
LVTTL/
LVDIFF
LVTTL
Input
FS
FBF0
Input
Input
3-level
Input
3-level
Input
Note:
1. For all three-state inputs, HIGH indicates a connection to V
CC
, LOW indicates a connection to GND, and MID indicates an open connection. Internal termination
circuitry holds an unconnected input to V
CC
/2.
Document #: 38-07127 Rev. *F
Page 3 of 15
RoboClock
CY7B993V
CY7B994V
Pin Definitions
(continued)
[1]
Pin Name
FBDS[0:1]
FBDIS
I/O
Input
Input
Pin Type
3-level
Input
LVTTL
Pin Description
Feedback Divider Function Select:
These inputs determine the function of the QFA0
and QFA1 outputs (see
Table 4).
Feedback Disable:
This input controls the state of QFA[0:1]. When HIGH, the QFA[0:1]
is disabled to the “HOLD-OFF” or “HI-Z” state; the disable state is determined by
OUTPUT_MODE. When LOW, the QFA[0:1] is enabled (see
Table 5).
This input has an
internal pull-down.
Output Phase Function Select:
Each pair controls the phase function of the respective
bank of outputs (see
Table 3).
Output Divider Function Select:
Each pair controls the divider function of the respective
bank of outputs (see
Table 4).
Output Disable:
Each input controls the state of the respective output bank. When HIGH,
the output bank is disabled to the “HOLD-OFF” or “HI-Z” state; the disable state is deter-
mined by OUTPUT_MODE. When LOW, the [1:4]Q[A:B][0:1] is enabled (see
Table 5).
These inputs each have an internal pull-down.
Invert Mode:
This input only affects Bank 3. When this input is LOW, each matched output
pair will become complementary (3QA0+, 3QA1–, 3QB0+, 3QB1–). When this input is
HIGH, all four outputs in the same bank will be inverted. When this input is MID all four
outputs will be non inverting.
PLL Lock Indicator:
When HIGH, this output indicates the internal PLL is locked to the
reference signal. When LOW, the PLL is attempting to acquire lock.
Output Mode:
This pin determines the clock outputs’ disable state. When this input is
HIGH, the clock outputs will disable to high-impedance (HI-Z). When this input is LOW,
the clock outputs will disable to “HOLD-OFF” mode. When in MID, the device will enter
factory test mode.
Clock Feedback Output:
This pair of clock outputs is intended to be connected to the
FB input. These outputs have numerous divide options and three choices of phase adjust-
ments. The function is determined by the setting of the FBDS[0:1] pins and FBF0.
Clock Output:
These outputs provide numerous divide and phase select functions deter-
mined by the [1:4]DS[0:1] and [1:4]F[0:1] inputs.
Output Buffer Power:
Power supply for each output pair.
Internal Power:
Power supply for the internal circuitry.
Device Ground.
The REF inputs can be changed dynamically. When changing
from one reference input to the other of the same frequency,
the PLL is optimized to ensure that the clock output period will
not be less than the calculated system budget (t
MIN
= t
REF
(nominal reference clock period) – t
CCJ
(cycle-to-cycle jitter) –
t
PDEV
(max. period deviation)) while reacquiring the lock.
VCO, Control Logic, Divider, and Phase Generator
The VCO accepts analog control inputs from the PLL filter
block. The FS control pin setting determines the nominal
operational frequency range of the divide by one output (f
NOM
)
of the device. f
NOM
is directly related to the VCO frequency.
There are two versions: a low-speed device (CY7B993V)
where f
NOM
ranges from 12 MHz to 100 MHz, and a
high-speed device (CY7B994V) that ranges from 24 MHz to
200 MHz. The FS setting for each device is shown in
Table 1.
The f
NOM
frequency is seen on “divide-by-one” outputs. For
the CY7B994V, the upper f
NOM
range extends from 96 MHz to
200 MHz.
[1:4]F[0:1]
[1:4]DS[0:1]
DIS[1:4]
Input
Input
Input
3-level
Input
3-level
Input
LVTTL
INV3
Input
3-level
Input
LOCK
Output LVTTL
3-Level
Input
OUTPUT_MODE Input
QFA[0:1]
Output LVTTL
[1:4]Q[A:B][0:1]
VCCN
VCCQ
GND
Output LVTTL
PWR
PWR
PWR
Block Diagram Description
Phase Frequency Detector and Filter
These two blocks accept signals from the REF inputs (REFA+,
REFA–, REFB+, or REFB–) and the FB inputs (FBKA+,
FBKA–, FBKB+, or FBKB–). Correction information is then
generated to control the frequency of the voltage-controlled
oscillator (VCO). These two blocks, along with the VCO, form
a PLL that tracks the incoming REF signal.
The CY7B993V/994V have a flexible REF and FB input
scheme. These inputs allow the use of either differential
LVPECL or single-ended LVTTL inputs. To configure as
single-ended LVTTL inputs, the complementary pin must be
left open (internally pulled to 1.5V). The other input pin can
then be used as an LVTTL input. The REF inputs are also
tolerant to hot insertion.
Document #: 38-07127 Rev. *F
Page 4 of 15
RoboClock
CY7B993V
CY7B994V
Table 1. Frequency Range Select
CY7B993V
f
NOM
(MHz)
FS
[2]
LOW
MID
HIGH
Min.
12
24
48
Max.
26
52
100
CY7B994V
f
NOM
(MHz)
Min.
24
48
96
Max.
52
100
200
[1:4]F1
Table 3. Output Skew Select Function
Function
Selects
[1:4]F0
and
FBF0
Output Skew Function
Feed-
back
Bank
Bank1
Bank2
Bank3
Bank4
LOW
LOW
LOW
MID
MID
MID
HIGH
HIGH
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
–4t
U
–3t
U
–2t
U
–1t
U
0t
U
+1t
U
+2t
U
+3t
U
+4t
U
–4t
U
–3tu
–2t
U
–1t
U
0t
U
+1t
U
+2t
U
+3t
U
+4t
U
–8t
U
–7t
U
–6t
U
BK1
[3]
0t
U
BK2
[3]
+6t
U
+7t
U
+8t
U
–8t
U
–7t
U
–6t
U
BK1
[3]
0t
U
BK2
[3]
+6t
U
+7t
U
+8t
U
–4t
U
NA
NA
NA
0tu
NA
NA
NA
+4t
U
Time Unit Definition
Selectable skew is in discrete increments of time unit (t
U
). The
value of a t
U
is determined by the FS setting and the maximum
nominal output frequency. The equation to be used to
determine the t
U
value is as follows:
t
U
= 1/(f
NOM
*N).
N is a multiplication factor which is determined by the FS
setting. f
NOM
is nominal frequency of the device. N is defined
in
Table 2.
Table 2. N Factor Determination
CY7B993V
FS
LOW
MID
HIGH
N
64
32
16
f
NOM
(MHz) at
which t
U
=1.0 ns
15.625
31.25
62.5
N
32
16
8
CY7B994V
f
NOM
(MHz) at
which t
U
=1.0 ns
31.25
62.5
125
Table 4. Output Divider Function
Function
Selects
[1:4]DS1
and
FBDS1
[1:4]DS0
and
FBDS0
Bank
1
Output Divider Function
Bank
2
Bank
3
Bank
4
Feed-
back
Bank
Divide and Phase Select Matrix
The Divide and Phase Select Matrix is comprised of five
independent banks: four banks of clock outputs and one bank
for feedback. Each clock output bank has two pairs of
low-skew, high-fanout output buffers ([1:4]Q[A:B][0:1]), two
phase function select inputs ([1:4]F[0:1]), two divider function
selects ([1:4]DS[0:1]), and one output disable (DIS[1:4]).
The feedback bank has one pair of low-skew, high-fanout
output buffers (QFA[0:1]). One of these outputs may connect
to the selected feedback input (FBK[A:B]±). This feedback
bank also has one phase function select input (FBF0), two
divider function selects FSDS[0:1], and one output disable
(FBDIS).
The phase capabilities that are chosen by the phase function
select pins are shown in
Table 3.
The divide capabilities for
each bank are shown in
Table 4.
LOW
LOW
LOW
MID
MID
MID
HIGH
HIGH
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
LOW
MID
HIGH
/1
/2
/3
/4
/5
/6
/8
/10
/12
/1
/2
/3
/4
/5
/6
/8
/10
/12
/1
/2
/3
/4
/5
/6
/8
/10
/12
/1
/2
/3
/4
/5
/6
/8
/10
/12
/1
/2
/3
/4
/5
/6
/8
/10
/12
Figure 1
illustrates the timing relationship of programmable
skew outputs. All times are measured with respect to REF with
the output used for feedback programmed with 0t
U
skew. The
PLL naturally aligns the rising edge of the FB input and REF
input. If the output used for feedback is programmed to
another skew position, then the whole t
U
matrix will shift with
respect to REF. For example, if the output used for feedback
is programmed to shift –8t
U
, then the whole matrix is shifted
forward in time by 8t
U
. Thus an output programmed with 8t
U
of skew will effectively be skewed 16t
U
with respect to REF.
Notes:
2. The level to be set on FS is determined by the “nominal” operating frequency (f
NOM
) of the V
CO
and Phase Generator. f
NOM
always appears on an output when
the output is operating in the undivided mode. The REF and FB are at f
NOM
when the output connected to FB is undivided.
3. BK1, BK2 denotes following the skew setting of Bank1 and Bank2, respectively.
Document #: 38-07127 Rev. *F
Page 5 of 15
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