SN74LVC2G32-EP
DUAL 2-INPUT POSITIVE-OR GATE
www.ti.com
SCES543A – FEBRUARY 2004 – REVISED AUGUST 2006
FEATURES
•
Controlled Baseline
– One Assembly/Test Site, One Fabrication
Site
Extended Temperature Performance of –55°C
to 125°C
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree
(1)
Supports 5-V V
CC
Operation
Inputs Accept Voltages to 5.5 V
Max t
pd
of 3.8 ns at 3.3 V
Low Power Consumption, 10-µA Max I
CC
±24-mA
Output Drive at 3.3 V
Typical V
OLP
(Output Ground Bounce)
<0.8 V at V
CC
= 3.3 V, T
A
= 25°C
Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
(1)
Typical V
OHV
(Output V
OH
Undershoot)
>2 V at V
CC
= 3.3 V, T
A
= 25°C
I
off
Supports Partial Power-Down-Mode
Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DCU PACKAGE
(TOP VIEW)
1A
1B
2Y
GND
1
2
3
4
8
7
6
5
V
CC
1Y
2B
2A
DESCRIPTION/ORDERING INFORMATION
This dual 2-input positive-OR gate is designed for 1.65-V to 5.5-V V
CC
operation.
The SN74LVC2G32 performs the Boolean function
Y
+
A
)
B or Y
+
A
•
B
in positive logic.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
T
A
–55°C to 125°C
(1)
(2)
SSOP – DCU
PACKAGE
(1)
Reel of 3000
ORDERABLE PART NUMBER
SN74LVC2G32MDCUREP
TOP-SIDE MARKING
(2)
BUE
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DCU: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
FUNCTION TABLE
(EACH GATE)
INPUTS
A
H
X
L
B
X
H
L
OUTPUT
Y
H
H
L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2006, Texas Instruments Incorporated
SN74LVC2G32-EP
DUAL 2-INPUT POSITIVE-OR GATE
SCES543A – FEBRUARY 2004 – REVISED AUGUST 2006
www.ti.com
LOGIC DIAGRAM (POSITIVE LOGIC)
1A
1B
2A
2B
1
2
5
6
7
1Y
3
2Y
Absolute Maximum Ratings
(1)
over operating free-air temperature range (unless otherwise noted)
MIN
V
CC
V
I
V
O
V
O
I
IK
I
OK
I
O
θ
JA
T
stg
(1)
(2)
(3)
(4)
Supply voltage range
Input voltage
range
(2)
Voltage range applied to any output in the high-impedance or power-off state
(2)
Voltage range applied to any output in the high or low state
(2) (3)
Input clamp current
Output clamp current
Continuous output current
Continuous current through V
CC
or GND
Package thermal
impedance
(4)
–65
Storage temperature range
V
I
< 0
V
O
< 0
–0.5
–0.5
–0.5
–0.5
MAX
6.5
6.5
6.5
V
CC
+ 0.5
–50
–50
±50
±100
220
150
UNIT
V
V
V
V
mA
mA
mA
mA
°C/W
°C
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
The value of V
CC
is provided in the recommended operating conditions table.
The package thermal impedance is calculated in accordance with JESD 51-7.
2
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SN74LVC2G32-EP
DUAL 2-INPUT POSITIVE-OR GATE
SCES543A – FEBRUARY 2004 – REVISED AUGUST 2006
Recommended Operating Conditions
(1)
MIN
V
CC
Supply voltage
Operating
Data retention only
V
CC
= 1.65 V to 1.95 V
V
IH
High-level input voltage
V
CC
= 2.3 V to 2.7 V
V
CC
= 3 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
CC
= 1.65 V to 1.95 V
V
IL
Low-level input voltage
V
CC
= 2.3 V to 2.7 V
V
CC
= 3 V to 3.6 V
V
CC
= 4.5 V to 5.5 V
V
I
V
O
Input voltage
Output voltage
V
CC
= 1.65 V
V
CC
= 2.3 V
I
OH
High-level output current
V
CC
= 3 V
V
CC
= 4.5 V
V
CC
= 1.65 V
V
CC
= 2.3 V
I
OL
Low-level output current
V
CC
= 3 V
V
CC
= 4.5 V
V
CC
= 1.8 V
±
0.15 V, 2.5 V
±
0.2 V
∆t/∆v
T
A
(1)
Input transition rise or fall rate
Operating free-air temperature
V
CC
= 3.3 V
±
0.3 V
V
CC
= 5 V
±
0.5 V
–55
0
0
1.65
1.5
0.65
×
V
CC
1.7
2
0.7
×
V
CC
0.35
×
V
CC
0.7
0.8
0.3
×
V
CC
5.5
V
CC
–4
–8
–16
–24
–32
4
8
16
24
32
20
10
5
125
°C
ns/V
mA
mA
V
V
V
V
MAX
5.5
UNIT
V
All unused inputs of the device must be held at V
CC
or GND to ensure proper device operation. See the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
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SN74LVC2G32-EP
DUAL 2-INPUT POSITIVE-OR GATE
SCES543A – FEBRUARY 2004 – REVISED AUGUST 2006
www.ti.com
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
I
OH
= –100
µA
I
OH
= –4 mA
V
OH
I
OH
= –8 mA
I
OH
= –16 mA
I
OH
= –24 mA
I
OH
= –32 mA
I
OL
= 100
µA
I
OL
= 4 mA
V
OL
I
OL
= 8 mA
I
OL
= 16 mA
I
OL
= 24 mA
I
OL
= 32 mA
I
I
I
off
I
CC
∆I
CC
C
i
(1)
A or B inputs
V
I
= 5.5 V or GND
V
I
or V
O
= 5.5 V
V
I
= 5.5 V or GND,
One input at V
CC
– 0.6 V,
V
I
= V
CC
or GND
All typical values are at V
CC
= 3.3 V, T
A
= 25°C.
I
O
= 0
Other inputs at V
CC
or GND
TEST CONDITIONS
V
CC
1.65 V to 5.5 V
1.65 V
2.3 V
3V
4.5 V
1.65 V to 5.5 V
1.65 V
2.3 V
3V
4.5 V
0 to 5.5 V
0
1.65 V to 5.5 V
3 V to 5.5 V
3.3 V
5
MIN TYP
(1)
V
CC
– 0.1
1.2
1.9
2.4
2.3
3.8
0.1
0.45
0.3
0.4
0.6
0.6
±5
±10
10
500
µA
µA
µA
µA
pF
V
V
MAX
UNIT
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see
Figure 1)
PARAMETER
t
pd
FROM
(INPUT)
A or B
TO
(OUTPUT)
Y
V
CC
= 1.8 V
±
0.15 V
MIN
2.4
MAX
11
V
CC
= 2.5 V
±
0.2 V
MIN
1
MAX
7.5
V
CC
= 3.3 V
±
0.3 V
MIN
1
MAX
5.8
V
CC
= 5 V
±
0.5 V
MIN
1
MAX
4.7
ns
UNIT
Operating Characteristics
T
A
= 25°C
PARAMETER
C
pd
Power dissipation capacitance
TEST CONDITIONS
f = 10 MHz
V
CC
= 1.8 V
TYP
17
V
CC
= 2.5 V
TYP
17
V
CC
= 3.3 V
TYP
17
V
CC
= 5 V
TYP
19
UNIT
pF
4
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SN74LVC2G32-EP
DUAL 2-INPUT POSITIVE-OR GATE
SCES543A – FEBRUARY 2004 – REVISED AUGUST 2006
PARAMETER MEASUREMENT INFORMATION
V
LOAD
From Output
Under Test
C
L
(see Note A)
R
L
S1
Open
GND
R
L
TEST
t
PLH
/t
PHL
t
PLZ
/t
PZL
t
PHZ
/t
PZH
S1
Open
V
LOAD
GND
LOAD CIRCUIT
INPUTS
V
CC
1.8 V
±
0.15 V
2.5 V
±
0.2 V
3.3 V
±
0.3 V
5 V
±
0.5 V
V
I
V
CC
V
CC
3V
V
CC
t
r
/t
f
≤2
ns
≤2
ns
≤2.5
ns
≤2.5
ns
V
M
V
CC
/2
V
CC
/2
1.5 V
V
CC
/2
V
LOAD
2
×
V
CC
2
×
V
CC
6V
2
×
V
CC
C
L
30 pF
30 pF
50 pF
50 pF
R
L
1 kΩ
500
Ω
500
Ω
500
Ω
V
∆
0.15 V
0.15 V
0.3 V
0.3 V
V
I
Timing Input
t
w
V
I
Input
V
M
V
M
0V
VOLTAGE WAVEFORMS
PULSE DURATION
V
I
Input
t
PLH
Output
t
PHL
V
M
V
M
V
M
V
M
0V
t
PHL
V
OH
V
M
V
OL
t
PLH
V
OH
Output
V
M
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Waveform 2
S1 at GND
(see Note B)
Output
Control
t
PZL
Output
Waveform 1
S1 at V
LOAD
(see Note B)
t
PZH
V
M
V
M
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
M
V
M
0V
t
PLZ
V
LOAD
/2
V
OL
+ V
∆
t
PHZ
V
OH
– V
∆
V
OH
≈0
V
V
OL
Data Input
t
su
V
M
t
h
V
I
V
M
0V
V
M
0V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C
L
includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤
10 MHz, Z
O
= 50
Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as t
en
.
G. t
PLH
and t
PHL
are the same as t
pd
.
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
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