Clock OSC
XG-2102CA
XG-2102CA 200.000000MHz +/-50ppm LGSN
Product name
X1M0003410024xx
Product Number / Ordering code
Please refer to the 9.Packing information about xx (last 2 digits)
Output waveform
LVDS
Pb free / Complies with EU RoHS directive
Reference weight Typ. 133 mg
1.Absolute maximum ratings
Parameter
Symbol
Maximum supply voltage
Storage temperature
Input voltage
Min.
-0.5
-55
0
Typ.
-
-
-
Max.
4
125
0
Unit
V
ºC
V
Conditions / Remarks
-
Storage as single product
ST or OE Terminal
Vcc-GND
T_stg
Vin
2.Specifications(characteristics)
Parameter
Symbol
Output frequency
Supply voltage
Operating temperature
Frequency tolerance
Current consumption
Stand-by current
Disable current
Symmetry
Output voltage(LVDS)
Min.
-
-0.5
-55
-50
-
-
-
45
247
-
1.125
-
-
0.7Vcc
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-10
-
Typ.
200.0000
-
-
-
-
-
-
-
-
-
-
-
100
-
-
-
-
-
-
-
-
-
-
-
-
-54.8
-82.0
-110.8
-139.2
-148.8
-151.0
-
-
Max.
-
4
125
50
30
-
15.0
55
454
50
1.375
150
-
-
0.3Vcc
0.4
0.4
10
N/A
N/A
N/A
N/A
N/A
0.23
-
-
-
-
-
-
-
10
-
Unit
MHz
V
ºC
x10
-6
mA
mA
mA
%
mV
mV
V
mV
Ω
Conditions / Remarks
Clock OSC
-
Storage as single product
-
-
-
-
-
-
-
-
-
-
-
-
Output load condition(LVDS)
Input voltage
Rise time
Fall time
Start-up time
Jitter
Phase jitter
Phase noise
f0
Vcc
T_use
f_tol
Icc
I_std
I_dis
SYM
V
OD
dV
OD
Vos
dVos
L_LVDS
V
IH
V
IL
t
r
tf
t_str
t
DJ
T
RJ
t
RMS
t
p-p
t
acc
t
PJ
L(f)
ps
ps
ms
ps
ps
ps
ps
ps
ps
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
-
-
-
Deterministic Jitter
Random Jitter
δ(RMS of total distribution)
Peak to Peak
Accumulated Jitter(δ) n=2 to 50000 cycles
Off set Frequency: 12kHz to 20MHz
Off set 1Hz
Off set 10Hz
Off set 100Hz
Off set 1kHz
Off set 10kHz
Off set 100kHz
Off set 1MHz
Frequency aging
f_age
x10
-6
/Year
@+25ºC first year
-
1 Page
3.Test circuit
1) To observe waveform and current (case 1)
A
+3.3 V
By-pass
capacitor 2
Power
supply 1
Vcc
OUT
OUT
Differentila probe
100 Ω
OE
OE pin*
NC
GND
Oscillo-
scope
By-pass
capacitor 1
* The lines from OUT and OUT pin are same length.
* To measure the disable current, OE pin is connected to GND
2) To observe waveform and current (case 2)
+3.3 V
By-pass
capacitor 2
Power
supply 1
Vcc
OUT
OUT
50 Ω
OE
OE pin
NC
GND
50 Ω
By-pass
capacitor 1
V
OD
V
V
V
OS
* The lines from OUT and OUT pin are same length.
3) Measurement condition
A) Oscilloscope
•Bandwidth should be 5 times higher than DUT’s output frequency (4 GHz).
•Probe ground should be placed closely from test point and lead length should be as short as possible.
B) By-pass capacitor 1 (approx. 0.01 μF to 0.1 μF) places closely between Vcc and GND.
C) By-pass capacitor 2 (approx. 10 μF) places closely between power supply terminals on the board.
D) Use the current meter whose internal impedance value is small.
E) Power supply
• Start up time (0 Vg90 %Vcc) of power source should be more than 150 μs and
slew rate should be less than 19.8 mV/μs.
• Impedance of power supply should be as low as possible.
2 Page
4.Timing chart
Each output waveform (OUT, and OUT)
Vcc
OUT
50 % of OUT
amplitude
50 % of OUT
amplitude
OUT
V
OS1
GND
V
OS2
tw
SYM = tw / t
t
Differential output waveform (OUT
–
OUT)
dV
OS
=½V
OS1
-V
OS2
½
tr
tf
80 % of amplitude
Differential
0V
OUT
V
OD1
V
OD2
OUT
20 % of amplitude
dV
OD
=½V
OD1
-V
OD2
½
5.External dimensions
#6
#5
#4
#4
(Unit: mm)
#5
#6
6.Footprint(Recommended)
1.1
1.6
(Unit: mm)
1.4
#1
#2
#3
7.0±0.
1.2±0.2
#3
2.54
#2
5.08
#1
3.9
E EG-4121
250.000H
GWA 282A
5.0±0.2
2.6
2.54
5.08
5.08
To maintain stable operation, provide a 0.01uF to 0.1uF
by-pass capacitor at a location as near as possible to the
power source terminal of the crystal product (between Vcc
- GND).
3 Page
1.5
7.Reflow profile
Reflow condition (Follow of JEDEC STD-020D.01)
Temperature[C]
300
250
200
150
100
50
Time
+25CtoPeak
0
60
120 180 240 300 360 420 480 540 600 660 720 780
Time[s]
;+217C
Tsmax;+200C
TL
TP
;+260C
+255C
Avg.
Ramp-up
3
C/sMax.
tp
;20sto40s
tL
60sto150s
(+217Cover)
Ramp-down
6C/sMax.
Tsmin;+150C
ts
60sto180s
(+150Cto+200C)
8.PCB layout (2 layers, 2nd layer is all GND pattern)
Terminators place near the input device.
LVDS termination
Line width (B) and Line space (S) is
εr : Relative dielectric constant of the board
H : Board thickness between line and GND
C : Line thickness
Two output lines are
same length and width
By-pass capacitor (approx. 10 μF)
places closely between power supply
By-pass capacitor (approx. 0.01 μF to 0.1 μF)
places closely between Vcc and GND
Connected to 2nd layer
GND through via-hole
4 Page
* By-pass capacitor (approx. 0.01 μF to 0.1 μF) places closely between Vcc and GND.
* By-pass capacitor (approx. 10 μF) places closely between power supply terminals on the board.
* Please design the two output lines by characteristic impedance 100 Ω and same length,
and try to make the output lines as short as possible.
9.Packing information
[ 1 ]Product number last 2 digits code(xx) description
The recommended code is "00"
Code
13
00
Condition
500pcs / Reel
1000pcs / Reel
X1M0003410024xx
Code
01
11
12
Condition
Any Q'ty vinyl bag(Tape cut)
Any Q'ty / Reel
250pcs / Reel
5 Page
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