TLK1501
0.6 TO 1.5 GBPS TRANSCEIVER
SLLS428F − JUNE 2000 − REVISED JANUARY 2004
D
Hot Plug Protection
D
0.6 to 1.5 Gigabits Per Second (Gbps)
D
D
D
D
D
Serializer/Deserializer
High-Performance 64-Pin VQFP Thermally
Enhanced Package (PowerPAD)
2.5 V Power Supply for Low Power
Operation
Programmable Voltage Output Swing on
Serial Output
Interfaces to Backplane, Copper Cables, or
Optical Converters
Rated for Industrial Temperature Range
D
On-Chip 8-Bit/10-Bit (8B/10B)
D
D
D
D
D
Encoding/Decoding, Comma Alignment,
and Link Synchronization
On-Chip PLL Provides Clock Synthesis
From Low-Speed Reference
Receiver Differential Input Thresholds
200 mV Minimum
Typical Power: 250 mW
Loss of Signal (LOS) Detection
Ideal for High-Speed Backplane
Interconnect and Point-to-Point Data Link
description
The TLK1501 is a member of the transceiver family of multigigabit transceivers used in ultrahigh-speed
bidirectional point-to-point data transmission systems. The TLK1501 supports an effective serial interface
speed of 0.6 Gbps to 1.5 Gbps, providing up to 1.2 Gbps of data bandwidth. The TLK1501 is pin-for-pin
compatible with the TLK2500. The TLK1501 is both pin-for-pin compatible with and functionally identical to the
TLK2501, a 1.6 to 2.5 Gbps transceiver, providing a wide range of performance solutions with no required board
layout changes.
The primary application of this chip is to provide very high-speed I/O data channels for point-to-point baseband
data transmission over controlled impedance media of approximately 50
Ω.
The transmission media can be
printed-circuit board, copper cables, or fiber-optic cable. The maximum rate and distance of data transfer is
dependent upon the attenuation characteristics of the media and the noise coupling to the environment.
This device can also be used to replace parallel data transmission architectures by providing a reduction in the
number of traces, connector terminals, and transmit/receive terminals. Parallel data loaded into the transmitter
is delivered to the receiver over a serial channel, which can be a coaxial copper cable, a controlled impedance
backplane, or an optical link. It is then reconstructed into its original parallel format. It offers significant power
and cost savings over current solutions, as well as scalability for higher data rate in the future.
The TLK1501 performs data conversion parallel-to-serial and serial-to-parallel. The clock extraction functions
as a physical layer interface device. The serial transceiver interface operates at a maximum speed of 1.5 Gbps.
The transmitter latches 16-bit parallel data at a rate based on the supplied reference clock (GTX_CLK). The
16-bit parallel data is internally encoded into 20 bits using an 8-bit/10-bit (8B/10B) encoding format. The
resulting 20-bit word is then transmitted differentially at 20 times the reference clock (GTX_CLK) rate. The
receiver section performs the serial-to-parallel conversion on the input data, synchronizing the resulting 20-bit
wide parallel data to the extracted reference clock (RX_CLK). It then decodes the 20 bit wide data using
8-bit/10-bit decoding format resulting in 16 bits of parallel data at the receive data terminals (RXD0-15). The
outcome is an effective data payload of 480 Mbps to 1.2 Gbps (16 bits data x the GTX_CLK frequency).
The TLK1501 is housed in a high performance, thermally enhanced, 64-pin VQFP PowerPAD package. Use
of the PowerPAD package does not require any special considerations except to note that the PowerPAD, which
is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor. It is
recommended that the TLK1501 PowerPAD be soldered to the thermal land on the board. All ac performance
specifications in this data sheet are measured with the PowerPAD soldered to the test board.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2000 − 2004, Texas Instruments Incorporated
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1
TLK1501
0.6 TO 1.5 GBPS TRANSCEIVER
SLLS428F − JUNE 2000 − REVISED JANUARY 2004
description (continued)
The TLK1501 provides an internal loopback capability for self-test purposes. Serial data from the serializer is
passed directly to the deserializer, allowing the protocol device a functional self-check of the physical interface.
The TLK1501 is designed to be hot plug capable. An on-chip power-on reset circuit holds the RX_CLK low
during power up. This circuit also holds the parallel side output signal terminals during power up as well as
DOUTTXP and DOUTTXN in a high-impedance state.
The TLK1501 has a loss of signal detection circuit for conditions where the incoming signal no longer has a
sufficient voltage amplitude to keep the clock recovery circuit in lock.
To prevent a data bit error from causing a valid data packet from being interpreted as a comma and thus causing
the erroneous word alignment by the comma detection circuit, the comma word alignment circuit is turned off
after the link is properly established in TLK1501.
The TLK1501 allows users to implement redundant ports by connecting receive data bus terminals from two
TLK1501 devices together. Asserting the LCKREFN to a low state causes the receive data bus terminals,
RXD[0:15], RX_CLK and RX_ER, RX_DV/LOS to go to a high-impedance state. This places the device in a
transmit-only mode, since the receiver is not tracking the data.
The TLK1501 uses a 2.5-V supply. The I/O section is 3 V compatible. With the 2.5-V supply the chipset is very
power-efficient, consuming less than 360 mW typically. The TLK1501 is characterized for operation from −40°C
to 85°C.
AVAILABLE OPTIONS
PACKAGE
TA
PowerPAD QUAD FLATPACK
(PQFP)
TLK1501IRCP
−40°C to 85°C
TLK1501IRCPR
2
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TLK1501
0.6 TO 1.5 GBPS TRANSCEIVER
SLLS428F − JUNE 2000 − REVISED JANUARY 2004
RCP PACKAGE
(TOP VIEW)
TXD2
TXD1
TXD0
GNDA
DOUTTXP
DOUTTXN
GNDA
VDDA
RREF
VDDA
DINRXP
DINRXN
GNDA
RXD0
V
DD
TXD3
TXD4
TXD5
GND
TXD6
TXD7
GTX_CLK
V
DD
TXD8
TXD9
TXD10
GND
TXD11
TXD12
TXD13
1
2
3
4
5
6
7
8
9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
RXD1
RXD2
V
DD
RXD3
RXD4
RXD5
RXD6
GND
RXD7
RX_CLK
RXD8
RXD9
V
DD
RXD10
RXD11
RXD12
RXD13
GND
10
11
12
13
14
15
33
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
TXD14
GND
TXD15
TX_EN
LOOPEN
TX_ER
V DD
ENABLE
LCKREFN
PRBSEN
TESTEN
GND
RX_ER/PRBS_PASS
RX_DV/LOS
RXD15
RXD14
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3
TLK1501
0.6 TO 1.5 GBPS TRANSCEIVER
SLLS428F − JUNE 2000 − REVISED JANUARY 2004
block diagram
LOOPEN
PRBSEN
TX_EN
TX_ER
PRBS
Generator
10
DOUTTXP
DOUTTXN
2:1
10
MUX
8B/10B
Encoder
Parallel to
Serial
BIAS
RREF
PRBSEN
8
TD(0−15)
16 Bit
Register
10
MUX
10
Bit
Clock
8
8B/10B
Encoder
10
GTX_CLK
TESTEN
ENABLE
PRBSEN
Controls:
PLL,Bias,Rx,
Tx
Multiplying
Clock
Synthesizer
Bit
Clock
RX_ER
PRBS_PASS
2:1
MUX
PRBSEN
Interpolator and
Clock Recovery
2:1
MUX
RX_CLK
RX_DV/LOS
PRBS
Verification
Recovered
Clock
8
16 Bit
Register
RD(0−15)
Comma
Detect
and 8B/10B
Decoding
Comma
Detect
and 8B/10B
Decoding
10
1:2
MUX
10
10
Serial to
Parallel
2:1 Data
MUX
DINRXP
DINRXN
8
Signal Detect
(LOS)
Figure 1. TLK1501 Block Diagram
4
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TLK1501
0.6 TO 1.5 GBPS TRANSCEIVER
SLLS428F − JUNE 2000 − REVISED JANUARY 2004
Terminal Functions
TERMINAL
NAME
DINRXN
DINRXP
DOUTTXN
DOUTTXP
NO.
53
54
59
60
TYPE
I
O
DESCRIPTION
Serial receive inputs. DINRXP and DINRXN together are the differential serial input interface from a
copper or an optical I/F module.
Serial transmit outputs (Hi-Z on power up). DOUTTXP and DOUTTXN are differential serial outputs that
interface to copper or an optical I/F module. These terminals transmit NRZ data at a rate of 20 times the
GTX_CLK value. DOUTTXP and DOUTTXN are put in a high-impedance state when LOOPEN is high
and are active when LOOPEN is low. During power-on reset these terminals are high impedance.
Device enable (w/pullup). When this terminal is held low, the device is placed in power-down mode. Only
the signal detect circuit on the serial receive pair is active. When asserted high while the device is in
power-down mode, the transceiver goes into power-on reset before beginning normal operation.
Digital logic ground. Provides a ground for the logic circuits and digital I/O buffers.
ENABLE
24
I
GND
5, 13,
18, 28,
33, 43
52, 58,
61
8
I
GNDA
GTX_CLK
Analog ground. GNDA provides a ground reference for the high-speed analog circuits, RX and TX.
Reference clock. GTX_CLK is a continuous external input clock that synchronizes the transmitter
interface signals TX_EN, TX_ER and TXD. The frequency range of GTX_CLK is 30 MHz to 75 MHz.
The transmitter uses the rising edge of this clock to register the 16-bit input data (TXD) for serialization.
Lock to reference (w/pullup). When LCKREFN is low, the receiver clock is frequency locked to
GTX_CLK. This places the device in a transmit only mode since the receiver is not tracking the data.
When LCKREFN is asserted low, the receive data bus terminals, RXD[0:15], RX_CLK and RX_ER,
RX_DV/LOS are in a high-impedance state.
When LCKREFN is deasserted high, the receiver is locked to the received data stream and must receive
valid codes from the synchronization state machine before the transmitter is enabled.
LCKREFN
25
I
LOOPEN
21
I
Loop enable (w/pulldown). When LOOPEN is active high, the internal loop-back path is activated. The
transmitted serial data is directly routed internally to the inputs of the receiver. This provides a self-test
capability in conjunction with the protocol device. The DOUTTXP and DOUTTXN outputs are held in a
high-impedance state during the loop-back test. LOOPEN is held low during standard operational state
with external serial outputs and inputs active.
PRBS test enable (w/pulldown). When asserted high results of pseudorandom bit stream (PRBS) tests
can be monitored on the RX_ER/PRBS_PASS terminal. A high on PRBS_PASS indicates that valid
PRBS is being received.
Reference resistor. The RREF terminal is used to connect to an external reference resistor. The other
side of the resistor is connected to analog VDD. The resistor is used to provide an accurate current
reference to the transmitter circuitry.
Receive data bus (Hi-Z on power up). These outputs carry 16-bit parallel data output from the transceiver
to the protocol device, synchronized to RX_CLK. The data is valid on the rising edge of RX_CLK as
shown in Figure 13. These terminals are in high-impedance state during power-on reset.
PRBSEN
26
I
RREF
56
I
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RXD6
RXD7
RXD8
RXD9
RXD10
RXD11
RXD12
RXD13
RXD14
RXD15
51
50
49
47
46
45
44
42
40
39
37
36
35
34
32
31
O
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•
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5
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