MC14093B
Quad 2-Input “NAND"
Schmitt Trigger
The MC14093B Schmitt trigger is constructed with MOS
P−channel and N−channel enhancement mode devices in a single
monolithic structure. These devices find primary use where low power
dissipation and/or high noise immunity is desired. The MC14093B
may be used in place of the MC14011B quad 2−input NAND gate for
enhanced noise immunity or to “square up” slowly changing
waveforms.
Features
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•
Supply Voltage Range = 3.0 Vdc to 18 Vdc
•
Capable of Driving Two Low−Power TTL Loads or One
•
•
•
•
•
•
Low−Power Schottky TTL Load Over the Rated Temperature
Range
Triple Diode Protection on All Inputs
Pin−for−Pin Compatible with CD4093
Can be Used to Replace MC14011B
Independent Schmitt−Trigger at each Input
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free and are RoHS Compliant
SOIC−14
D SUFFIX
CASE 751A
SOEIAJ−14
F SUFFIX
CASE 965
TSSOP−14
DT SUFFIX
CASE 948G
PIN ASSIGNMENT
IN 1
A
IN 2
A
OUT
A
OUT
B
IN 1
B
IN 2
B
V
SS
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
DD
IN 2
D
IN 1
D
OUT
D
OUT
C
IN 2
C
IN 1C
MAXIMUM RATINGS
(Voltages Referenced to V
SS
)
Symbol
V
DD
V
in
, V
out
I
in
, I
out
P
D
T
A
T
stg
T
L
Parameter
DC Supply Voltage Range
Input or Output Voltage Range
(DC or Transient)
Input or Output Current
(DC or Transient) per Pin
Power Dissipation,
per Package (Note 1)
Ambient Temperature Range
Storage Temperature Range
Lead Temperature
(8−Second Soldering)
Value
−0.5 to +18.0
−0.5 to V
DD
+ 0.5
±10
500
−55 to +125
−65 to +150
260
Unit
V
V
mA
mW
°C
°C
°C
1
14
MARKING DIAGRAMS
14
14093BG
AWLYWW
1
SOIC−14
14
14
093B
ALYW
G
G
1
TSSOP−14
A
WL, L
YY, Y
WW, W
G or
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
SOEIAJ−14
MC14093B
ALYWG
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. Temperature Derating: “D/DW” Packages: –7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high−impedance circuit. For proper operation, V
in
and V
out
should be constrained
to the range V
SS
≤
(V
in
or V
out
)
≤
V
DD
.
Unused inputs must always be tied to an appropriate logic voltage level
(e.g., either V
SS
or V
DD
). Unused outputs must be left open.
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
©
Semiconductor Components Industries, LLC, 2014
1
August, 2014 − Rev. 10
Publication Order Number:
MC14093B/D
MC14093B
ELECTRICAL CHARACTERISTICS
(Voltages Referenced to V
SS
)
−55_C
Characteristic
Output Voltage
V
in
= V
DD
or 0
“0” Level
Symbol
V
OL
V
DD
Vdc
5.0
10
15
5.0
10
15
5.0
5.0
10
15
I
OL
5.0
10
15
15
−
5.0
10
15
5.0
10
15
Min
−
−
−
4.95
9.95
14.95
–3.0
–0.64
–1.6
–4.2
0.64
1.6
4.2
−
−
−
−
−
Max
0.05
0.05
0.05
−
−
−
−
−
−
−
−
−
−
±0.1
−
0.25
0.5
1.0
Min
−
−
−
4.95
9.95
14.95
–2.4
–0.51
–1.3
–3.4
0.51
1.3
3.4
−
−
−
−
−
25_C
Typ
(Note 2)
0
0
0
5.0
10
15
–4.2
–0.88
–2.25
–8.8
0.88
2.25
8.8
±0.00001
5.0
0.0005
0.0010
0.0015
Max
0.05
0.05
0.05
−
−
−
−
−
−
−
−
−
−
±0.1
7.5
0.25
0.5
1.0
125_C
Min
−
−
−
4.95
9.95
14.95
–1.7
–0.36
–0.9
–2.4
0.36
0.9
2.4
−
−
−
−
−
Max
0.05
0.05
0.05
−
−
−
−
−
−
−
−
−
−
±1.0
−
7.5
15
30
mAdc
Unit
Vdc
“1” Level
V
in
= 0 or V
DD
Output Drive Current
(V
OH
= 2.5 Vdc)
(V
OH
= 4.6 Vdc)
(V
OH
= 9.5 Vdc)
(V
OH
= 13.5 Vdc)
(V
OL
= 0.4 Vdc)
(V
OL
= 0.5 Vdc)
(V
OL
= 1.5 Vdc)
Input Current
Input Capacitance
(V
in
= 0)
Quiescent Current
(Per Package)
Total Supply Current (Notes 3 & 4)
(Dynamic plus Quiescent,
Per Package)
(C
L
= 50 pF on all outputs, all
buffers switching)
Hysteresis Voltage
V
OH
Vdc
I
OH
Source
mAdc
Sink
I
in
C
in
I
DD
mAdc
pF
mAdc
I
T
I
T
= (1.2
mA/kHz)
f + I
DD
I
T
= (2.4
mA/kHz)
f + I
DD
I
T
= (3.6
mA/kHz)
f + I
DD
mAdc
V
H
†
5.0
10
15
5.0
10
15
5.0
10
15
0.3
1.2
1.6
2.2
4.6
6.8
0.9
2.5
4.0
2.0
3.4
5.0
3.6
7.1
10.8
2.8
5.2
7.4
0.3
1.2
1.6
2.2
4.6
6.8
0.9
2.5
4.0
1.1
1.7
2.1
2.9
5.9
8.8
1.9
3.9
5.8
2.0
3.4
5.0
3.6
7.1
10.8
2.8
5.2
7.4
0.3
1.2
1.6
2.2
4.6
6.8
0.9
2.5
4.0
2.0
3.4
5.0
3.6
7.1
10.8
2.8
5.2
7.4
Vdc
Threshold Voltage
Positive−Going
Vdc
V
T+
Negative−Going
V
T–
Vdc
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
3. The formulas given are for the typical characteristics only at 25_C.
4. To calculate total supply current at loads other than 50 pF:
I
T
(C
L
) = I
T
(50 pF) + (C
L
– 50) Vfk
where: I
T
is in
mA
(per package), C
L
in pF, V = (V
DD
– V
SS
) in volts, f in kHz is input frequency, and k = 0.004.
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3
MC14093B
SWITCHING CHARACTERISTICS
(C
L
= 50 pF, T
A
= 25_C)
Characteristic
Output Rise Time
Symbol
t
TLH
V
DD
Vdc
5.0
10
15
5.0
10
15
5.0
10
15
Min
−
−
−
−
−
−
−
−
−
Typ
(Note 5)
100
50
40
100
50
40
125
50
40
Max
200
100
80
200
100
80
250
100
80
Unit
ns
Output Fall Time
t
THL
ns
Propagation Delay Time
t
PLH
, t
PHL
ns
5. Data labeled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
V
DD
14
PULSE
GENERATOR
OUTPUT
INPUT
7
V
SS
20 ns
INPUT
t
PHL
C
L
OUTPUT
90%
50%
10%
t
THL
t
TLH
90%
50%
10%
20 ns
V
DD
V
SS
V
OH
V
OL
t
PLH
Figure 1. Switching Time Test Circuit and Waveforms
V
H
V
in
V
DD
V
in
V
SS
V
DD
V
H
V
DD
V
SS
V
DD
V
out
V
SS
V
out
V
SS
(a) Schmitt Triggers will square up
(a)
inputs with slow rise and fall times.
(b) A Schmitt trigger offers maximum
(b)
noise immunity in gate applications.
Figure 2. Typical Schmitt Trigger Applications
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MC14093B
14
I
OH
V
out
All unused inputs
connected to ground.
0
V
GS
= - 5.0 Vdc
a
b
b
T
A
= - 55°C
T
A
= + 25°C
T
A
= + 125°C
c
- 10 Vdc
- 8.0
b
7
V
GS
c
b
IOL , DRAIN CURRENT (mAdc)
a
10
a
All unused inputs
connected to ground.
b c
a
b
6.0
c
a
b
c
a
b
c
a
- 2.0
0
0
0
2.0
4.0
6.0
V
DS
, DRAIN VOLTAGE (Vdc)
8.0
10
5.0 Vdc
T
A
= - 55°C
T
A
= + 25°C
T
A
= + 125°C
15 Vdc
V
GS
= 10 Vdc
14
V
GS
7
I
OL
V
out
IOH, DRAIN CURRENT (mAdc)
- 2.0
8.0
- 4.0
- 6.0
4.0
c
b
- 15 Vdc
2.0
- 10
- 10
a
- 8.0
- 6.0
- 4.0
V
DS
, DRAIN VOLTAGE (Vdc)
Figure 3. Typical Output Source
Characteristics Test Circuit
Figure 4. Typical Output Sink
Characteristics Test Circuit
V
DD
Vout , OUTPUT VOLTAGE (Vdc)
0
0
V
T-
V
H
V
T+
V
DD
V
in
, INPUT VOLTAGE (Vdc)
Figure 5. Typical Transfer Characteristics
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