ADS1274
ADS1278
www.ti.com
SBAS367F
–
JUNE 2007
–
REVISED FEBRUARY 2011
Quad/Octal, Simultaneous Sampling, 24-Bit Analog-to-Digital Converters
Check for Samples:
ADS1274, ADS1278
1
FEATURES
DESCRIPTION
Based on the single-channel
ADS1271,
the ADS1274
(quad) and ADS1278 (octal) are 24-bit, delta-sigma
(ΔΣ) analog-to-digital converters (ADCs) with data
rates up to 144k samples per second (SPS), allowing
simultaneous sampling of four or eight channels. The
devices are offered in identical packages, permitting
drop-in expandability.
Traditionally, industrial delta-sigma ADCs offering
good drift performance use digital filters with large
passband droop. As a result, they have limited signal
bandwidth and are mostly suited for dc
measurements. High-resolution ADCs in audio
applications offer larger usable bandwidths, but the
offset and drift specifications are significantly weaker
than respective industrial counterparts. The ADS1274
and ADS1278 combine these types of converters,
allowing high-precision industrial measurement with
excellent dc and ac specifications.
The
high-order,
chopper-stabilized
modulator
achieves very low drift with low in-band noise. The
onboard decimation filter suppresses modulator and
signal out-of-band noise. These ADCs provide a
usable signal bandwidth up to 90% of the Nyquist
rate with less than 0.005dB of ripple.
Four operating modes allow for optimization of speed,
resolution, and power. All operations are controlled
directly by pins; there are no registers to program.
The devices are fully specified over the extended
industrial range (–40°C to +105°C) and are available
in an HTQFP-64 PowerPAD™ package.
IOVDD
VREFP VREFN AVDD
DVDD
IOVDD
•
Simultaneously Measure Four/Eight Channels
•
Up to 144kSPS Data Rate
•
AC Performance:
70kHz Bandwidth
111dB SNR (High-Resolution Mode)
–108dB
THD
•
DC Accuracy:
0.8μV/°C Offset Drift
1.3ppm/°C Gain Drift
•
Selectable Operating Modes:
High-Speed: 144kSPS, 106dB SNR
High-Resolution: 52kSPS, 111dB SNR
Low-Power: 52kSPS, 31mW/ch
Low-Speed: 10kSPS, 7mW/ch
•
Linear Phase Digital Filter
•
SPI™ or Frame-Sync Serial Interface
•
Low Sampling Aperture Error
•
Modulator Output Option (digital filter bypass)
•
Analog Supply: 5V
•
Digital Core: 1.8V
•
I/O Supply: 1.8V to 3.3V
234
APPLICATIONS
•
•
•
•
Vibration/Modal Analysis
Multi-Channel Data Acquisition
Acoustics/Dynamic Strain Gauges
Pressure Sensors
VREFP VREFN
AVDD
DVDD
Input1
Input2
Input3
Input4
DS
DS
DS
DS
Four
Digital
Filters
SPI
and
Frame-
Sync
Interface
DRDY/FSYNC
SCLK
DOUT[4:1]
DIN
TEST[1:0]
FORMAT[2:0]
CLK
SYNC
PWDN[4:1]
CLKDIV
MODE[1:0]
Input1
Input2
Input3
Input4
Input5
Input6
Input7
Input8
DS
DS
DS
DS
DS
DS
DS
DS
AGND
Eight
Digital
Filters
SPI
and
Frame-
Sync
Interface
DRDY/FSYNC
SCLK
DOUT[8:1]
DIN
TEST[1:0]
FORMAT[2:0]
CLK
SYNC
PWDN[8:1]
CLKDIV
MODE[1:0]
Control
Logic
Control
Logic
AGND
DGND
DGND
ADS1274
ADS1278
1
2
3
4
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments, Inc.
SPI is a trademark of Motorola, Inc.
All other trademarks are the property of their respective owners.
©
2007–2011, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
ADS1274
ADS1278
SBAS367F
–
JUNE 2007
–
REVISED FEBRUARY 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
For the most current package and ordering information, see the Package Option Addendum at the end of this
document, or visit the device product folder at
www.ti.com.
ABSOLUTE MAXIMUM RATINGS
Over operating free-air temperature range unless otherwise noted
(1)
ADS1274, ADS1278
AVDD to AGND
DVDD, IOVDD to DGND
AGND to DGND
Input current
Analog input to AGND
Digital input or output to DGND
Maximum junction temperature
Operating temperature range
Storage temperature range
(1)
ADS1274
ADS1278
Momentary
Continuous
–0.3
to +6.0
–0.3
to +3.6
–0.3
to +0.3
100
10
–0.3
to AVDD + 0.3
–0.3
to IOVDD + 0.3
+150
–40
to +125
–40
to +105
–60
to +150
UNIT
V
V
V
mA
mA
V
V
°C
°C
°C
°C
Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
2
Submit Documentation Feedback
Product Folder Link(s):
ADS1274 ADS1278
©
2007–2011, Texas Instruments Incorporated
ADS1274
ADS1278
www.ti.com
SBAS367F
–
JUNE 2007
–
REVISED FEBRUARY 2011
ELECTRICAL CHARACTERISTICS
All specifications at T
A
=
–40°C
to +105°C, AVDD = +5V, DVDD = +1.8V, IOVDD = +3.3V, f
CLK
= 27MHz, VREFP = 2.5V,
VREFN = 0V, and all channels active, unless otherwise noted.
ADS1274, ADS1278
PARAMETER
ANALOG INPUTS
Full-scale input voltage (FSR
(1)
)
Absolute input voltage
Common-mode input voltage (V
CM
)
High-Speed mode
Differential input impedance
High-Resolution mode
Low-Power mode
Low-Speed mode
DC PERFORMANCE
Resolution
High-Speed mode
(2)
Data rate (f
DATA
)
No missing codes
f
CLK
= 37MHz
f
CLK
= 32.768MHz
f
CLK
= 27MHz
High-Resolution mode
Low-Power mode
Low-Speed mode
Integral nonlinearity (INL)
(4)
Offset error
Offset drift
Gain error
Gain drift
High-Speed mode
Noise
High-Resolution mode
Low-Power mode
Low-Speed mode
Common-mode rejection
AVDD
Power-supply rejection
DVDD
IOVDD
V
COM
output voltage
No load
f
PS
= 60Hz
Shorted input
Shorted input
Shorted input
Shorted input
f
CM
= 60Hz
90
Differential input, V
CM
= 2.5V
24
144,531
128,000
105,469
52,734
52,734
10,547
±0.0003
0.25
0.8
0.1
1.3
8.5
5.5
8.5
8.0
108
80
85
105
AVDD/2
16
12
16
16
0.5
±0.0012
2
Bits
SPS
(3)
SPS
SPS
SPS
SPS
SPS
% FSR
(1)
mV
μV/°C
% FSR
ppm/°C
μV,
rms
μV,
rms
μV,
rms
μV,
rms
dB
dB
dB
dB
V
V
IN
= (AINP
–
AINN)
AINP or AINN to AGND
V
CM
= (AINP + AINN)/2
AGND
–
0.1
2.5
14
14
28
140
±V
REF
AVDD + 0.1
V
V
V
kΩ
kΩ
kΩ
kΩ
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(1)
(2)
(3)
(4)
FSR = full-scale range = 2V
REF
.
f
CLK
= 37MHz max for High-Speed mode, and 27MHz max for all other modes. See
Table 7
for f
CLK
restrictions in High-Speed mode.
SPS = samples per second.
Best fit method.
©
2007–2011, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s):
ADS1274 ADS1278
3
ADS1274
ADS1278
SBAS367F
–
JUNE 2007
–
REVISED FEBRUARY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
All specifications at T
A
=
–40°C
to +105°C, AVDD = +5V, DVDD = +1.8V, IOVDD = +3.3V, f
CLK
= 27MHz, VREFP = 2.5V,
VREFN = 0V, and all channels active, unless otherwise noted.
ADS1274, ADS1278
PARAMETER
AC PERFORMANCE
Crosstalk
High-Speed mode
Signal-to-noise ratio (SNR)
(6)
(unweighted)
High-Resolution mode
Low-Power mode
Low-Speed mode
Total harmonic distortion (THD)
(7)
Spurious-free dynamic range
Passband ripple
Passband
–3dB
Bandwidth
Stop band attenuation
High-Resolution mode
All other modes
High-Resolution mode
All other modes
High-Resolution mode
All other modes
High-Resolution mode
All other modes
Complete settling
Complete settling
95
100
0.547 f
DATA
0.547 f
DATA
39/f
DATA
38/f
DATA
78/f
DATA
76/f
DATA
AGND
–
0.1
0.1
≤
f
CLK
≤
27MHz
27
<
f
CLK
≤
32.768MHz
32.768MHz
<
f
CLK
≤
37MHz
High-Speed mode
ADS1274
Reference Input impedance
High-Resolution mode
Low-Power mode
Low-Speed mode
High-Speed mode
ADS1278
Reference Input impedance
High-Resolution mode
Low-Power mode
Low-Speed mode
DIGITAL INPUT/OUTPUT (IOVDD = 1.8V to 3.6V)
V
IH
V
IL
V
OH
V
OL
Input leakage
Master clock rate (f
CLK
)
I
OH
= 4mA
I
OL
= 4mA
0
<
V
IN DIGITAL
<
IOVDD
High-Speed mode
Other modes
(8)
TEST CONDITIONS
f = 1kHz,
–0.5dBFS
(5)
MIN
TYP
MAX
UNIT
–107
101
106
110
111
101
101
106
107
–108
109
±0.005
0.453 f
DATA
0.49 f
DATA
–96
dB
dB
dB
dB
dB
dB
dB
dB
dB
Hz
Hz
dB
V
REF
= 2.5V
V
REF
= 3V
103
V
IN
= 1kHz,
–0.5dBFS
Stop band
127.453 f
DATA
63.453 f
DATA
Hz
Hz
s
s
s
s
Group delay
Settling time (latency)
VOLTAGE REFERENCE INPUTS
Negative reference input (VREFN)
Reference input voltage (V
REF
)
(8)
(V
REF
= VREFP
–
VREFN)
AGND + 0.1
2.5
2.5
2.048
1.3
1.3
2.6
13
0.65
0.65
1.3
6.5
3.1
2.6
2.1
V
V
V
V
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
0.5
0.5
0.5
0.7 IOVDD
DGND
0.8 IOVDD
DGND
IOVDD
0.3 IOVDD
IOVDD
0.2 IOVDD
±10
V
V
V
V
μA
MHz
MHz
0.1
0.1
37
27
(5)
(6)
(7)
(8)
Worst-case channel crosstalk between one or more channels.
Minimum SNR is ensured by the limit of the
DC noise
specification.
THD includes the first nine harmonics of the input signal; Low-Speed mode includes the first five harmonics.
f
CLK
= 37MHz max for High-Speed mode, and 27MHz max for all other modes. See
Table 7
for V
REF
restrictions in High-Speed mode.
4
Submit Documentation Feedback
Product Folder Link(s):
ADS1274 ADS1278
©
2007–2011, Texas Instruments Incorporated
ADS1274
ADS1278
www.ti.com
SBAS367F
–
JUNE 2007
–
REVISED FEBRUARY 2011
ELECTRICAL CHARACTERISTICS (continued)
All specifications at T
A
=
–40°C
to +105°C, AVDD = +5V, DVDD = +1.8V, IOVDD = +3.3V, f
CLK
= 27MHz, VREFP = 2.5V,
VREFN = 0V, and all channels active, unless otherwise noted.
ADS1274, ADS1278
PARAMETER
POWER SUPPLY
AVDD
DVDD
(9)
IOVDD
AVDD
Power-down current
DVDD
IOVDD
ADS1274
High-Speed mode
ADS1274
AVDD current
High-Resolution mode
Low-Power mode
Low-Speed mode
High-Speed mode
ADS1274
DVDD current
High-Resolution mode
Low-Power mode
Low-Speed mode
High-Speed mode
ADS1274
IOVDD current
High-Resolution mode
Low-Power mode
Low-Speed mode
High-Speed mode
ADS1274
Power dissipation
High-Resolution mode
Low-Power mode
Low-Speed mode
ADS1278
High-Speed mode
ADS1278
AVDD current
High-Resolution mode
Low-Power mode
Low-Speed mode
High-Speed mode
ADS1278
DVDD current
High-Resolution mode
Low-Power mode
Low-Speed mode
High-Speed mode
ADS1278
IOVDD current
High-Resolution mode
Low-Power mode
Low-Speed mode
High-Speed mode
ADS1278
Power dissipation
High-Resolution mode
Low-Power mode
Low-Speed mode
97
97
44
9
23
16
12
2.5
0.25
0.125
0.125
0.035
530
515
245
50
145
145
64
14
30
20
17
4.5
1
0.5
0.5
0.2
785
765
355
80
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mW
mW
mW
mW
50
50
23
5
18
12
10
2.5
0.15
0.075
0.075
0.02
285
275
135
30
75
75
35
9
24
17
15
4.5
0.5
0.3
0.3
0.15
420
410
210
55
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mW
mW
mW
mW
0.1
≤
f
CLK
≤
32.768MHz
32.768MHz
<
f
CLK
≤
37MHz
4.75
1.65
2.0
1.65
1
1
1
5
1.8
2.1
5.25
1.95
2.2
3.6
10
15
10
V
V
V
V
μA
μA
μA
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(9)
f
CLK
= 37MHz max for High-Speed mode, and 27MHz max for all other modes. See
Table 7
for DVDD restrictions in High-Speed mode.
©
2007–2011, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Link(s):
ADS1274 ADS1278
5
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