CY62128DV30
1-Mb (128K x 8) Static RAM
Features
• Very high speed: 55 and 70 ns
• Wide voltage range: 2.2V to 3.6V
• Pin compatible with CY62128V
• Ultra-low active power
— Typical active current: 0.85 mA @ f = 1 MHz
— Typical active current: 5 mA @ f = f
MAX
• Ultra-low standby power
• Easy memory expansion with CE
1
, CE
2
, and OE
features
• Automatic power-down when deselected
• Available in Pb-free and non Pb-free 32-lead SOIC,
32-lead TSOP and 32-lead Small TSOP, non Pb-free
32-lead Reverse TSOP packages
also has an automatic power-down feature that significantly
reduces power consumption by 90% when addresses are not
toggling. The device can be put into standby mode reducing
power consumption by more than 99% when deselected Chip
Enable 1 (CE
1
) HIGH or Chip Enable 2 (CE
2
) LOW. The
input/output pins (I/O
0
through I/O
7
) are placed in a
high-impedance state when: deselected Chip Enable 1 (CE
1
)
HIGH or Chip Enable 2 (CE
2
) LOW, outputs are disabled (OE
HIGH), or during a write operation (Chip Enable 1 (CE
1
) LOW
and Chip Enable 2 (CE
2
) HIGH and Write Enable (WE) LOW).
Writing to the device is accomplished by taking Chip Enable 1
(CE
1
) LOW with Chip Enable 2 (CE
2
) HIGH and Write Enable
(WE) LOW. Data on the eight I/O pins is then written into the
location specified on the Address pin (A
0
through A
16
).
Reading from the device is accomplished by taking Chip
Enable 1 (CE
1
) LOW with Chip Enable 2 (CE
2
) HIGH and
Output Enable (OE) LOW while forcing the Write Enable (WE)
HIGH. Under these conditions, the contents of the memory
location specified by the address pins will appear on the I/O
pins.
The eight input/output pins (I/O
o
through I/O
7
) are placed in a
high-impedance state when the device is deselected (CE
1
HIGH or CE
2
LOW), the outputs are disabled (OE HIGH) or
during a write operation (CE
1
LOW, CE
2
HIGH), and WE
LOW).
Functional Description
[1]
The CY62128DV30 is a high-performance CMOS static RAM
organized as 128K words by 8 bits. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL
®
) in
portable applications such as cellular telephones. The device
Logic Block Diagram
Data in Drivers
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
ROW DECODER
I/O0
I/O1
SENSE AMPS
I/O2
I/O3
I/O4
I/O5
128K x 8
ARRAY
CE
1
CE
2
WE
COLUMN
DECODER
Power-
down
I/O6
I/O7
A 12
A 13
A 14
OE
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
A 15
A 16
Cypress Semiconductor Corporation
Document #: 38-05231 Rev. *H
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 19, 2006
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CY62128DV30
Pin Configurations
[2]
Top View
SOIC
DNU
A
16
A
14
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
A
15
CE
2
WE
A
13
A
8
A
9
A
11
OE
A
10
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
A
11
A
9
A
8
A
13
WE
CE
2
A
15
V
CC
DNU
A
16
A
14
A
12
A
7
A
6
A
5
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
TSOP I
Top View
(not to scale)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A
10
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
A
3
A
11
A
9
A
8
A
13
WE
CE
2
A
15
V
CC
DNU
A
16
A
14
A
12
A
7
A
6
A
5
A
4
25
26
27
26
28
29
30
31
32
1
2
3
4
5
6
7
8
STSOP
Top View
(not to scale)
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
OE
A
10
CE
1
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
12
A
14
A
16
DNU
V
CC
A
15
CE
2
WE
A
13
A
8
A
9
A
11
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Reverse TSOP I
Top View
(not to scale)
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
GND
I/O
3
I/O
4
I/O
5
I/O
6
I/O
7
CE
1
A
10
OE
Product Portfolio
Power Dissipation
Operating, I
CC
(mA)
V
CC
Range (V)
Product
CY62128DV30L
CY62128DV30LL
Min.
2.2
Typ.
3.0
Max.
3.6
Speed
(ns)
55/70
55/70
f = 1 MHz
Typ.
[4]
0.85
0.85
Max.
1.5
1.5
5
5
f = f
MAX
Typ.
[4]
Max.
10
10
Standby, I
SB2
(µA)
Typ.
[4]
1.5
1.5
Max.
5
4
Notes:
2. NC pins are not connected to the die.
3. DNU pins have to be left floating or tied to Vss to ensure proper application.
4. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V
CC
= V
CC(typ)
, T
A
= 25°C.
Document #: 38-05231 Rev. *H
Page 2 of 11
[+] Feedback
CY62128DV30
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage to Ground
Potential ..........................................................
−0.3V
to 3.9V
DC Voltage Applied to Outputs
in High-Z State
[5]
....................................−0.3V to V
CC
+ 0.3V
DC Input Voltage
[5]
................................
−0.3V
to V
CC
+ 0.3V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage........................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... > 200 mA
Operating Range
Range
Industrial
Ambient
Temperature (T
A
)
−40°C
to +85°C
V
CC
[6]
2.2V to 3.6V
DC Electrical Characteristics
(Over the Operating Range)
CY62128DV30-55/70
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
V
CC
Operating Supply
Current
Automatic CE Power-down
Current
−
CMOS Inputs
Test Conditions
2.2 < V
CC
< 2.7
2.7 < V
CC
< 3.6
2.2 < V
CC
< 2.7
2.7 < V
CC
< 3.6
2.2 < V
CC
< 2.7
2.7 < V
CC
< 3.6
2.2 < V
CC
< 2.7
2.7 < V
CC
< 3.6
GND < V
I
< V
CC
GND < V
O
< V
CC
, Output Disabled
f = f
MAX
= 1/t
RC
f = 1 MHz
V
CC
= 3.6V,
I
OUT
= 0mA,
CMOS level
I
OH
=
−0.1
mA
I
OH
=
−1.0
mA
I
OL
= 0.1 mA
I
OL
= 2.1 mA
1.8
2.2
−0.3
−0.3
−1
−1
5
0.85
1.5
1.5
1.5
1.5
Min.
2.0
2.4
0.4
0.4
V
CC
+ 0.3
V
CC
+ 0.3
0.6
0.8
+1
+1
10
1.5
5
4
5
4
µA
µA
µA
µA
mA
V
V
V
Typ.
[4]
Max.
Unit
V
I
SB1
CE
1
> V
CC
−
0.2V, CE
2
< 0.2V,
L
V
IN
> V
CC
−
0.2V, V
IN
< 0.2V,
LL
f = f
MAX
(Address and Data Only),
f = 0 (OE, WE,)
CE
1
> V
CC
−
0.2V, CE
2
< 0.2V,
V
IN
> V
CC
−
0.2V or V
IN
< 0.2V,
f = 0, V
CC
=3.6V
L
LL
I
SB2
Automatic CE Power-down
Current
−
CMOS Inputs
Capacitance
[7]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz
V
CC
= V
CC(typ)
Max.
8
8
Unit
pF
pF
Thermal Resistance
[7]
Parameter
θ
JA
θ
JC
Description
Thermal Resistance
(Junction to Ambient)
Test Conditions
SOIC TSOP I RTSOP STSOP
69
34
93
17
93
17
65
15
Unit
°C/W
°C/W
Still Air, soldered on a 3 x 4.5
inch, two-layer printed circuit
Thermal Resistance (Junction to Case) board
Notes:
5. V
IL(min.)
=
−2.0V
for pulse durations less than 20 ns. V
IH(max.)
= V
CC
+0.75V for pulse durations less than 20 ns
.
6. Full device operation requires linear ramp of V
CC
from 0V to V
CC(min)
and V
CC
must be stable at V
CC(min)
for 500
µ
s.
7. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05231 Rev. *H
Page 3 of 11
[+] Feedback
CY62128DV30
AC Test Loads and Waveforms
[8]
R1
V
CC
OUTPUT
50 pF
INCLUDING
JIG AND
SCOPE
R2
V
CC
10%
GND
Rise Time = 1 V/ns
ALL INPUT PULSES
90%
90%
10%
Fall Time = 1 V/ns
Equivalent to: THEVENIN EQUIVALENT
R
TH
OUTPUT
V
2.5V (2.2V - 2.7V)
16600
15400
8000
1.20
3.0V (2.7V - 3.6V)
1103
1554
645
1.75
Unit
Ω
Ω
Ω
V
Parameters
R1
R2
R
TH
V
TH
Data Retention Characteristics
Parameter
V
DR
I
CCDR
t
CDR
t
R
[8]
[4]
Description
V
CC
for Data Retention
Data Retention Current
Chip Deselect to Data Retention Time
Operation Recovery Time
Conditions
V
CC
= 1.5V, CE
1
> V
CC
−
0.2V, CE
2
< 0.2V, L
V
IN
> V
CC
−
0.2V or V
IN
< 0.2V
LL
Min.
1.5
Typ.
[4]
Max. Unit
V
4
3
µA
ns
µs
0
100
Data Retention Waveform
DATA RETENTION MODE
V
CC
CE
1
V
CC(min.)
t
CDR
V
DR
> 1.5V
V
CC(min.)
t
R
or
CE
2
Note:
8. Full device operation requires linear V
CC
ramp from V
DR
to V
CC(min.)
> 100
µs.
Document #: 38-05231 Rev. *H
Page 4 of 11
[+] Feedback
CY62128DV30
Switching Characteristics
(Over the Operating Range)
[9]
CY62128DV30-55
Parameter
Read Cycle
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
Write Cycle
[12]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
HZWE
t
LZWE
Write Cycle Time
CE
1
LOW or CE
2
HIGH to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
Data Set-up to Write End
Data Hold from Write End
WE LOW to High Z
[10, 11]
WE HIGH to Low Z
[10]
10
55
40
40
0
0
40
25
0
20
10
70
60
60
0
0
50
30
0
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
1
LOW or CE
2
HIGH to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
[10]
OE HIGH to High Z
[10, 11]
CE
1
LOW or CE
2
HIGH to Low Z
[10]
CE
1
HIGH or CE
2
LOW to High Z
[10, 11]
CE
1
LOW or CE
2
HIGH to Power-up
CE
1
HIGH or CE
2
LOW to Power-down
0
55
10
20
0
70
5
20
10
25
10
55
25
5
25
55
55
10
70
35
70
70
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
CY62128DV30-70
Min.
Max.
Unit
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)
[13, 14]
t
RC
ADDRESS
t
AA
t
OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
Notes:
9. Test conditions assume signal transition time of 1V/ns or less, timing reference levels of V
CC(typ.)
/2, input pulse levels of 0 to V
CC(typ.)
, and output loading of
the specified I
OL
.
10. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZBE
is less than t
LZBE
, t
HZOE
is less than t.
11. t
HZOE
, t
HZCE
, t
HZBE
, and t
HZWE
transitions are measured when the outputs enter a high-impedance state.
12. The internal write time of the memory is defined by the overlap of WE, CE
1
= V
IL
, and CE
2
= V
IH
. All signals.
13. Device is continuously selected. OE, CE
1
= V
IL
, CE
2
= V
IH
.
14. WE is HIGH for Read cycle.
Document #: 38-05231 Rev. *H
Page 5 of 11
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