— One input drives nine outputs, grouped as 4 + 4 + 1
(CY2309)
•
Compatible with
Pentium
-based systems
• Test Mode to bypass phase-locked loop (PLL) (CY2309
only [see “Select Input Decoding” on page 2])
• Available in space-saving 16-pin 150-mil SOIC or
4.4-mm TSSOP packages (CY2309), and 8-pin, 150-mil
SOIC package (CY2305)
• 3.3V operation
• Industrial temperature available
CY2309. It accepts one reference input, and drives out five
low-skew clocks. The -1H versions of each device operate at
up to 100-/133-MHz frequencies, and have higher drive than
the -1 devices. All parts have on-chip PLLs which lock to an
input clock on the REF pin. The PLL feedback is on-chip and
is obtained from the CLKOUT pad.
The CY2309 has two banks of four outputs each, which can
be controlled by the Select inputs as shown in the “Select Input
Decoding” table on page 2. If all output clocks are not required,
BankB can be three-stated. The select inputs also allow the
input clock to be directly applied to the outputs for chip and
system testing purposes.
The CY2305 and CY2309 PLLs enter a power-down mode
when there are no rising edges on the REF input. In this state,
the outputs are three-stated and the PLL is turned off, resulting
in less than 12.0
µA
of current draw for commercial temper-
ature devices and 25.0
µA
for industrial temperature parts. The
CY2309 PLL shuts down in one additional case as shown in
the table below.
Multiple CY2305 and CY2309 devices can accept the same
input clock and distribute it. In this case, the skew between the
outputs of two devices is guaranteed to be less than 700 ps.
The CY2305/CY2309 is available in two/three different config-
urations, as shown in the ordering information (page 10). The
CY2305-1/CY2309-1 is the base part. The CY2305-1H/
CY2309-1H is the high-drive version of the -1, and its rise and
fall times are much faster than the -1s.
Functional Description
The CY2309 is a low-cost 3.3V zero delay buffer designed to
distribute high-speed clocks and is available in a 16-pin SOIC
or TSSOP package. The CY2305 is an 8-pin version of the
Block Diagram
Pin Configuration
SOIC/TSSOP
Top View
REF
CLKA1
CLKA2
V
DD
GND
CLKB1
CLKB2
S2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PLL
REF
MUX
CLKOUT
CLKA1
CLKA2
CLKA3
CLKA4
CLKOUT
CLKA4
CLKA3
V
DD
GND
CLKB4
CLKB3
S1
S2
Select Input
Decoding
S1
CLKB1
CLKB2
CLKB3
CLKB4
REF
CLK2
CLK1
GND
1
2
3
4
SOIC
Top View
8
7
6
5
CLKOUT
CLK4
V
DD
CLK3
Cypress Semiconductor Corporation
Document #: 38-07140 Rev. *G
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised August 4, 2005
CY2305
CY2309
Pin Description for CY2309
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
REF
[1]
CLKA1
V
DD
GND
CLKB1
[2]
CLKB2
[2]
S2
[3]
S1
[3]
CLKB3
GND
V
DD
CLKA3
[2]
CLKA4
[2]
CLKOUT
[2]
[2]
[2]
Signal
Buffered clock output, Bank A
Buffered clock output, Bank A
3.3V supply
Ground
Buffered clock output, Bank B
Buffered clock output, Bank B
Select input, bit 2
Select input, bit 1
Buffered clock output, Bank B
Buffered clock output, Bank B
Ground
3.3V supply
Buffered clock output, Bank A
Buffered clock output, Bank A
Description
Input reference frequency, 5V-tolerant input
CLKA2
[2]
CLKB4
[2]
Buffered output, internal feedback on this pin
Pin Description for CY2305
Pin
1
2
3
4
5
6
7
8
REF
[1]
CLK2
[2]
CLK1
[2]
GND
CLK3
[2]
V
DD
CLK4
[2]
CLKOUT
[2]
Signal
Buffered clock output
Buffered clock output
Ground
Buffered clock output
3.3V supply
Buffered clock output
Buffered clock output, internal feedback on this pin
Description
Input reference frequency, 5V-tolerant input
Select Input Decoding for CY2309
S2
0
0
1
1
S1
0
1
0
1
CLOCK A1–A4
Three-state
Driven
Driven
Driven
CLOCK B1–B4
Three-state
Three-state
Driven
Driven
CLKOUT
[4]
Driven
Driven
Driven
Driven
Output Source
PLL
PLL
Reference
PLL
PLL Shutdown
N
N
Y
N
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-ups on these inputs.
4. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and output.
Document #: 38-07140 Rev. *G
Page 2 of 14
CY2305
CY2309
REF. Input to CLKA/CLKB Delay vs. Loading Difference between CLKOUT and CLKA/CLKB Pins
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve Zero Delay
between the input and output. Since the CLKOUT pin is the
internal feedback to the PLL, its relative loading can adjust the
input-output delay. This is shown in the above graph.
For applications requiring zero input-output delay, all outputs,
including CLKOUT, must be equally loaded. Even if CLKOUT
is not used, it must have a capacitive load, equal to that on
other outputs, for obtaining zero input-output delay. If input to
output delay adjustments are required, use the above graph to
calculate loading differences between the CLKOUT pin and
other outputs.
For zero output-output skew, be sure to load all outputs
equally. For further information refer to the application note
entitled “CY2305 and CY2309 as PCI and SDRAM Buffers.”
Document #: 38-07140 Rev. *G
Page 3 of 14
CY2305
CY2309
Absolute Maximum Conditions
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
DC Input Voltage (Except REF) ............–0.5V to V
DD
+ 0.5V
DC Input Voltage REF......................................... –0.5V to 7V
Storage Temperature ................................. –65°C to +150°C
Junction Temperature ................................................. 150°C
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