EQTG32C2JH-13.66667M
REGULATORY COMPLIANCE
2011/65 +
2015/863
(Data Sheet downloaded on Sep 1, 2020)
191 SVHC
ITEM DESCRIPTION
Temperature Compensated Quartz Crystal Clock Oscillators TCXO LVPECL (PECL) 2.5Vdc 6 Pad 2.5mm x 3.2mm Ceramic
Surface Mount (SMD) 13.66667MHz -10°C to +60°C
ELECTRICAL SPECIFICATIONS
Nominal Frequency
Frequency Stability
Frequency Stability vs. Frequency
Tolerance
Frequency Stability vs. Input Voltage
Frequency Stability vs. Load
Frequency Stability vs. Reflow
Frequency Stability vs. Aging
Operating Temperature Range
Supply Voltage
Input Current
Output Voltage Logic High (Voh)
Output Voltage Logic Low (Vol)
Rise/Fall Time
Duty Cycle
Load Drive Capability
Output Logic Type
Phase Noise
13.66667MHz
±1.0ppm Maximum (Inclusive of Operating Temperature Range, at Vdd=2.5Vdc)
±2.0ppm Maximum (at 25°C ±2°C, at Vdd=2.5Vdc, Pre-Reflow)
±0.2ppm Maximum (±5%)
±0.2ppm Maximum (±2pF)
±1.0ppm Maximum (at 25°C, 24 hours after reflow, 1 time)
±1ppm/Year Maximum (at 25°C)
-10°C to +60°C
2.5Vdc ±5%
75mA Maximum
Vdd-1.025Vdc Minimum, 1.6Vdc Typical, Vdd-0.6Vdc Maximum
Vdd-1.85Vdc Minimum, 0.8Vdc Typical, Vdd-1.62Vdc Maximum
300pSec Maximum (Measured at 10% to 90% of Waveform)
50 ±5(%) (Measured at 50% of Waveform)
50 Ohms into Vdd-2Vdc
LVPECL
-64dBc/Hz at 10Hz offset; -96dBc/Hz at 100Hz offset; -124dBc/Hz at 1kHz offset; -131dBc/Hz at 10kHz offset; -
132dBc/Hz at 100kHz offset; -149dBc/Hz at 1MHz offset; -157dBc/Hz at 10MHz offset; -159dBc/Hz at 20MHz offset (All
Values are Typical)
Output Enable (OE)
90% of Vdd Minimum or No Connect to Enable Output and Complementary Output
10% of Vdd Maximum to Disable Output and Complementary Output (High Impedance)
100nSec Maximum
50nSec Maximum
15mA Maximum (Without Load (Pin 2 = Ground))
1.5pSec Maximum (Fj=12kHz to 20MHz (Random))
0.2pSec Typical
2pSec Typical
3pSec Maximum
30pSec Maximum
10mSec Maximum
-55°C to +125°C
Output Control Function
Output Control Input Voltage Logic
High (Vih)
Output Control Input Voltage Logic
Low (Vil)
Output Enable Time
Output Disable Time
Output Enable Current
RMS Phase Jitter
Period Jitter (Deterministic)
Period Jitter (Random)
Period Jitter (RMS)
Period Jitter (pk-pk)
Start Up Time
Storage Temperature Range
www.ecliptek.com | Specification Subject to Change Without Notice | Revision A 09/09/2015 | Page 1 of 7
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
EQTG32C2JH-13.66667M
ENVIRONMENTAL & MECHANICAL SPECIFICATIONS
ESD Susceptibility
Fine Leak Test
Flammability
Gross Leak Test
Mechanical Shock
Moisture Resistance
Moisture Sensitivity
Resistance to Soldering Heat
Resistance to Solvents
Solderability
Temperature Cycling
Vibration
MIL-STD-883, Method 3015, Class 1, HBM: 1500V
MIL-STD-883, Method 1014, Condition A
UL94-V0
MIL-STD-883, Method 1014, Condition C
MIL-STD-883, Method 2002, Condition B
MIL-STD-883, Method 1004
J-STD-020, MSL 1
MIL-STD-202, Method 210, Condition K
MIL-STD-202, Method 215
MIL-STD-883, Method 2003
MIL-STD-883, Method 1010, Condition B
MIL-STD-883, Method 2007, Condition A
www.ecliptek.com | Specification Subject to Change Without Notice | Revision A 09/09/2015 | Page 2 of 7
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
EQTG32C2JH-13.66667M
MECHANICAL DIMENSIONS (all dimensions in millimeters)
PIN
CONNECTION
Do Not Connect
Output Enable (OE)
Case/Ground
Output
Complementary Output
Supply Voltage
0.80 ±0.10 (X4)
2.50
±0.10
1.70
MAX
1.285
±0.10
3
3.20
±0.10
2.57
±0.10
2
1
0.90 ±0.10
1.55
±0.10
4
0.50
±0.10 (X2)
MARKING
ORIENTATION
1
2
3
4
5
6
0.475
±0.10 (X2)
5
6
0.55
±0.10 (X4)
LINE MARKING
1
2
E13.666
E=Ecliptek Designator
XXXXX
XXXXX=Ecliptek
Manufacturing Identifier
Terminal Plating Thickness:
Gold (0.3 to 1.0µm) over Nickel (1.27 to 8.89µm).
Suggested Solder Pad Layout
All Dimensions in Millimeters
2.50
±0.10
1.10 (X4)
1.70
MAX
0.90
±0.10
3
2.57
±0.10
0.70 (X2)
0.75 (X6)
4
5
6
0.55
±0.10 (X4)
0.50
±0.10 (X2)
0.80
±0.10
(X4)
3.20
±0.10
MARKING
0.60 (X4)
ORIENTATION
2
1
0.50 (X2)
Solder Land
(X6)
1.285 ±0.10
1.55
±0.10
All Tolerances are ±0.1
www.ecliptek.com | Specification Subject to Change Without Notice | Revision A 09/09/2015 | Page 3 of 7
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
EQTG32C2JH-13.66667M
OUTPUT WAVEFORM & TIMING DIAGRAM
V
IH
INPUT
V
IL
Q & Q OUTPUTS
V
OH
80%
50%
20%
V
OL
Q
OUTPUT DISABLE
(HIGH IMPEDANCE
STATE)
Q
t
PLZ
Fall
Time
Rise
Time
T
W
T
Duty Cycle (%) = T
W
/T x 100
t
PZL
www.ecliptek.com | Specification Subject to Change Without Notice | Revision A 09/09/2015 | Page 4 of 7
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
EQTG32C2JH-13.66667M
Test Circuit for PECL Output
50 Ohms
Oscilloscope
Frequency
Counter
Power
Supply
Supply
Voltage
(V
DD
)
Current
Meter
0.01µF
(Note 1)
0.1µF
(Note 1)
Complementary
Output
Probe 2
(Note 2)
Output
Probe 1
(Note 2)
50 Ohms
Switch
Power
Supply
Voltage
Meter
Power
Supply
Ground
Do Not
Connect
Output
Enable
Power
Supply
Note 1: An external 0.01µF ceramic bypass capacitor in parallel with a 0.1µF high frequency ceramic bypass capacitor close (less than 2mm)
to the package ground and supply voltage pin is required.
Note 2: A low capacitance (<12pF), 10X attenuation factor, high impedance (>10Mohms), and high bandwidth (>500MHz) passive probe is
recommended.
Note 3: Test circuit PCB traces need to be designed for a characteristic line impedance of 50 ohms.
www.ecliptek.com | Specification Subject to Change Without Notice | Revision A 09/09/2015 | Page 5 of 7
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
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