LPC2104/2105/2106
Single-chip 32-bit microcontrollers; 128 kB ISP/IAP Flash with
64 kB/32 kB/16 kB RAM
Rev. 02 — 11 June 2003
Product data
1. General description
The LPC2104, 2105 and 2106 are based on a 16/32 bit ARM7TDMI-S CPU with
real-time emulation and embedded trace support, together with 128 kbytes (kB) of
embedded high speed flash memory. A 128 bit wide memory interface and a unique
accelerator architecture enable 32 bit code execution at maximum clock rate. For
critical code size applications, the alternative 16-bit Thumb Mode reduces code by
more than 30% with minimal performance penalty.
Due to their tiny size and low power consumption, these microcontrollers are ideal for
applications where miniaturization is a key requirement, such as access control and
point-of-sale. With a wide range of serial communications interfaces and on-chip
SRAM options up to 64 kilobytes, they are very well suited for communication
gateways and protocol converters, soft modems, voice recognition and low end
imaging, providing both large buffer size and high processing power. Various 32 bit
timers, PWM channels and 32 GPIO lines make these microcontrollers particularly
suitable for industrial control and medical systems.
2. Features
2.1 Key features
s
16/32 bit ARM7TDMI-S processor.
s
16/32/64 kB on-chip Static RAM.
s
128 kB on-chip Flash Program Memory. 128 bit wide interface/accelerator
enables high speed 60 MHz operation.
s
In-System Programming (ISP) and In-Application Programming (IAP) via on-chip
boot-loader software. Flash programming takes 1 ms per 512 byte line. Single
sector or full chip erase takes 400 ms.
s
Vectored Interrupt Controller with configurable priorities and vector addresses.
s
EmbeddedICE-RT interface enables breakpoints and watchpoints. Interrupt
service routines can continue to execute whilst the foreground task is debugged
with the on-chip RealMonitor software.
s
Embedded Trace Macrocell enables non-intrusive high speed real-time tracing of
instruction execution.
s
Multiple serial interfaces including two UARTs (16C550), Fast I
2
C (400 kbits/s)
and SPI.
s
Two 32-bit timers (7 capture/compare channels), PWM unit (6 outputs), Real Time
Clock and Watchdog.
s
Up to thirty-two 5 V tolerant general purpose I/O pins in a tiny LQFP48
(7
×
7 mm
2
) package.
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
s
60 MHz maximum CPU clock available from programmable on-chip
Phase-Locked Loop.
s
On-chip crystal oscillator with an operating range of 10 MHz to 25 MHz.
s
Two low power modes, Idle and Power-down.
s
Processor wake-up from Power-down mode via external interrupt.
s
Individual enable/disable of peripheral functions for power optimization.
s
Dual power supply:
x
CPU operating voltage range of 1.65 V to 1.95 V (1.8 V
±8.3%).
x
I/O power supply range of 3.0 V to 3.6 V (3.3 V
±10%)
with 5 V tolerant I/O
pads.
3. Ordering information
Table 1:
Ordering information
Package
Name
LPC2104BBD48
LPC2105BBD48
LPC2106BBD48
LQFP48
LQFP48
LQFP48
Description
Version
plastic low profile quad flat package, 48 leads, SOT313-2
body 7
×
7
×
1.4 mm
plastic low profile quad flat package, 48 leads, SOT313-2
body 7
×
7
×
1.4 mm
plastic low profile quad flat package, 48 leads, SOT313-2
body 7
×
7
×
1.4 mm
Type number
3.1 Ordering options
Table 2:
Part options
Flash memory
128 kB
128 kB
128 kB
RAM
16 kB
32 kB
64 kB
Temperature range
0 to +70, LQFP
0 to +70, LQFP
0 to +70, LQFP
Type number
LPC2104BBD48
LPC2105BBD48
LPC2106BBD48
9397 750 11499
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 — 11 June 2003
2 of 34
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
4. Block diagram
TRST(1)
TMS(1)
TCK(1)
TDI(1)
TDO(1)
RTCK
XTAL1
PLL
system
clock
TEST/DEBUG
INTERFACE
EMULATION TRACE
MODULE
SYSTEM
FUNCTIONS
ARM7TDMI-S
AHB BRIDGE
ARM7 LOCAL BUS
VECTORED INTERRUPT
CONTROLLER
AMBA AHB
(Advanced High-performance Bus)
INTERNAL SRAM
CONTROLLER
INTERNAL
FLASH
CONTROLLER
AHB TO VPB
VPB
BRIDGE
DIVIDER
AHB
DECODER
16/32/64 kB
SRAM
128 kB
FLASH
APB(2)
EINT0*
EINT1*
EINT2*
EXTERNAL
INTERRUPTS
I2C SERIAL
INTERFACE
SCL*
SDA*
CAP0..2*
MAT0..2*
CAPTURE/
COMPARE
TIMER 0
SPI SERIAL
INTERFACE
CAP0..3*
MAT0..3*
CAPTURE/
COMPARE
TIMER 1
UART0
GPIO (32 PINS)
GENERAL
PURPOSE I/O
UART1
PWM1..6*
PWM0
WATCHDOG
TIMER
REAL TIME
CLOCK
SYSTEM
CONTROL
*Shared with GPIO
(1) When test/debug interface is used, GPIO/other function sharing these pins are not available.
(2) APB with Ready signal.
Fig 1. Block diagram.
9397 750 11499
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 — 11 June 2003
XTAL2
RST
VDD
VSS
SCK*
MOSI*
MISO*
SSEL*
TxD*
RxD*
TxD*
RxD*
MODEM CONTROL
(6 PINS)*
002aaa412
3 of 34
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
5. Pinning information
5.1 Pinning
46 P0.16/EINT0/MAT0.2
handbook, full pagewidth
P0.19/MAT1.2/TCK
P0.20/MAT1.3/TDI
P0.21/PWM5/TDO
NC
VDD1.8 (CORE)
RST
VSS1
P0.27/TRACEPKT0/TRST
P0.28/TRACEPKT1/TMS
1
2
3
4
5
6
37 P0.12/DSR1/MAT1.0
41 P0.13/DTR1/MAT1.1
47 P0.17/CAP1.2/TRST
39 P0.26/TRACESYNC
48 P0.18/CAP1.3/TMS
44 P0.14/DCD1/EINT1
38 P0.25/PIPESTAT2
45 P0.15/RI1/EINT2
40 VDD3-1 (I/O)
43 VSS4
42 NC
36 P0.11/CTS1/CAP1.1
35 P0.10/RTS1/CAP1.0
34 P0.24/PIPESTAT1
33 P0.23/PIPESTAT0
32 P0.22/TRACECLK
31 VSS3
30 P0.9/RxD1/PWM6
29 P0.8/TxD1/PWM4
28 P0.7/SSEL/PWM2
27 DBGSEL
26 RTCK
25 NC
LPC2104/2105/2106
7
8
9
P0.29/TRACEPKT2/TCK 10
X1 11
X2 12
P0.0/TxD0/PWM1 13
P0.1/RxD0/PWM3 14
P0.30/TRACEPKT3/TDI 15
P0.31/EXTIN0/TDO 16
VDD3-2 (I/O) 17
P0.2/SCL/CAP0.0 18
VSS2 19
NC 20
P0.3/SDA/MAT0.0 21
P0.4/SCK/CAP0.1 22
P0.5/MISO/MAT0.1 23
P0.6/MOSI/CAP0.2 24
002aaa411
Fig 2. Pinning.
9397 750 11499
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 — 11 June 2003
4 of 34
Philips Semiconductors
LPC2104/2105/2106
Single-chip 32-bit microcontrollers
5.2 Pin description
Table 3:
Symbol
P0.0 to P0.31
Pin description
Pin
Type
Description
Port 0:
Port 0 is a 32-bit bi-directional I/O port with individual direction
controls for each bit. The operation of port 0 pins depends upon the pin
function selected via the Pin Connect Block.
13, 14, 18,
I/O
21-24, 28-30,
35-37, 41,
44-48, 1-3,
32-34, 38,
39, 8-10, 15,
16
13
I/O
O
O
14
I/O
I
O
18
I/O
I/O
I
21
I/O
I/O
O
22
I/O
I/O
I
23
I/O
I/O
O
24
I/O
I/O
I
28
I/O
I
O
29
I/O
O
O
P0.0 —
Port 0 bit 0.
TxD0 —
Transmitter output for UART 0.
PWM1 —
Pulse Width Modulator output 1.
P0.1 —
Port 0 bit 1.
RxD0 —
Receiver input for UART 0.
PWM3 —
Pulse Width Modulator output 3.
P0.2 —
Port 0 bit 2.
SCL —
I
2
C clock input/output. Open drain output (for I
2
C compliance).
CAP0.0 —
Capture input for Timer 0, channel 0.
P0.3 —
Port 0 bit 3.
SDA —
I
2
C data input/output. Open drain output (for I
2
C compliance).
MAT0.0 —
Match output for Timer 0, channel 0.
P0.4 —
Port 0 bit 4.
SCK —
Serial clock. SPI clock output from master or input to slave.
CAP0.1 —
Capture input for Timer 0, channel 1.
P0.5 —
Port 0 bit 5.
MISO —
Master In Slave Out. Data input to SPI master or data output from
SPI slave.
MAT0.1 —
Match output for Timer 0, channel 1.
P0.6 —
Port 0 bit 6.
MOSI —
Master Out Slave In. Data output from SPI master or data input to
SPI slave.
CAP0.2 —
Capture input for Timer 0, channel 2.
P0.7 —
Port 0 bit 7.
SSEL —
Slave Select. Selects the SPI interface as a slave.
PWM2 —
Pulse Width Modulator output 2.
P0.8 —
Port 0 bit 8.
TxD1 —
Transmitter output for UART 1.
PWM4 —
Pulse Width Modulator output 4.
9397 750 11499
© Koninklijke Philips Electronics N.V. 2003. All rights reserved.
Product data
Rev. 02 — 11 June 2003
5 of 34
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