and above. (2) LSB means Least Significant Bit, with V
REFH
equal to +1.25V and V
REFL
equal to 0V, one LSB
is 0.305mV. (3) All DAC outputs will match within the specified error band. (4) Ideal output voltage does not take into account zero or full-scale error.
To
±0.012%
Full-Scale Step
On Any Other DAC
Bandwidth: 0Hz to 1MHz
CONDITIONS
MIN
TYP
MAX
±2
±2
±1
12
Code = 00A
H
5
±1
Code = FFF
H
±1
30
V
REFL
–625
No Oscillation
100
+8, –2
Indefinite
0
0
5
0.1
65
CMOS
| I
IH
|
≤
10µA
| I
IL
|
≤
10µA
V
DD
• 0.7
V
DD
–0.3
V
DD
• 0.3
Straight Binary
3.0
3.3
0.8
2.4
3.6
1
3
+85
T
T
T
T
T
T
T
T
T
T
T
V
mA
mW
°C
+1.25
T
T
T
T
T
T
T
T
V
V
±2.4
10
±2
±2.4
±2
T
T
T
T
T
T
T
T
T
T
T
T
T
±1.2
T
±1.2
MIN
DAC7617EB, UB
TYP
MAX
±1
±1
±1
UNITS
LSB
(2)
LSB
LSB
Bits
mV
ppm/°C
mV
mV
mV
ppm/V
V
µA
pF
mA
V
REFH
+625
T
T
V
V
µs
LSB
nV/√Hz
10
T
–40
T
2
DAC7617
SBAS185
ABSOLUTE MAXIMUM RATINGS
(1)
V
DD
to GND ........................................................................ –0.3V to +5.5V
V
REFL
to GND ........................................................... –0.3V to (V
DD
+ 0.3V)
V
DD
to V
REFH
.......................................................................... –0.3V to V
DD
V
REFH
to V
REFL
........................................................................ –0.3V to V
DD
Digital Input Voltage to GND ...................................... –0.3V to V
DD
+ 0.3V
Maximum Junction Temperature ................................................... +150°C
Operating Temperature Range ......................................... –40°C to +85°C
Storage Temperature Range .......................................... –65°C to +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
NOTE: (1) Stresses above those listed under “Absolute Maximum Ratings” may
cause permanent damage to the device. Exposure to absolute maximum
conditions for extended periods may affect device reliability.
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas Instru-
ments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet its published
specifications.
PACKAGE/ORDERING INFORMATION
MAXIMUM
LINEARITY
ERROR
(LSB)
±2
MAXIMUM
DIFFERENTIAL
LINEARITY
(LSB)
±1
PACKAGE
DRAWING
NUMBER
211
SPECIFICATION
TEMPERATURE
RANGE
–40°C to +85°C
PRODUCT
DAC7617U
PACKAGE
SO-16
ORDERING
NUMBER
(1)
DAC7617U
DAC7617U/1K
DAC7617UB
DAC7617UB/1K
DAC7617E
DAC7617E/1K
DAC7617EB
DAC7617EB/1K
TRANSPORT
MEDIA
Rails
Tape and Reel
Rails
Tape and Reel
Rails
Tape and Reel
Rails
Tape and Reel
"
DAC7617UB
"
±1
"
±1
"
SO-16
"
211
"
–40°C to +85°C
"
DAC7617E
"
±2
"
±1
"
SSOP-20
"
334
"
–40°C to +85°C
"
DAC7617EB
"
±1
"
±1
"
SSOP-20
"
334
"
–40°C to +85°C
"
"
"
"
"
"
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /1K indicates 1000 devices per reel). Ordering 1000 pieces
of “DAC7617EB/1K” will get a single 1000-piece Tape and Reel.
DAC7617
SBAS185
3
PIN CONFIGURATION—U Package
Top View
SO
PIN CONFIGURATION—E Package
Top View
SSOP
V
DD
V
DD
V
OUTD
V
OUTC
V
REFL
V
REFH
V
OUTB
V
OUTA
AGND
1
2
3
4
DAC7617U
5
6
7
8
12
11
10
9
CS
CLK
SDI
GND
NIC
V
REFH
V
OUTB
V
OUTA
16
15
14
13
RESETSEL
RESET
LOADREG
LDAC
V
OUTD
V
OUTC
V
REFL
NIC
1
2
3
4
5
DAC7617E
6
7
8
9
20
19
18
17
16
15
14
13
12
11
RESETSEL
RESET
LOADREG
LDAC
NIC
NIC
CS
CLK
SDI
GND
AGND 10
PIN DESCRIPTIONS—U Package
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
LABEL
V
DD
V
OUTD
V
OUTC
V
REFL
V
REFH
V
OUTB
V
OUTA
AGND
GND
SDI
CLK
CS
LDAC
DESCRIPTION
Positive Analog Supply Voltage, +3V nominal.
DAC D Voltage Output
DAC C Voltage Output
Reference Input Voltage Low. Sets minimum out-
put voltage for all DACs.
Reference Input Voltage High. Sets maximum out-
put voltage for all DACs.
DAC B Voltage Output
DAC A Voltage Output
Analog Ground
Ground
Serial Data Input
Serial Data Clock
Chip Select Input
All DAC registers become transparent when LDAC
is LOW. They are in the latched state when LDAC
is HIGH.
The selected input register becomes transparent
when LOADREG is LOW. It is in the latched state
when LOADREG is HIGH.
Asynchronous Reset Input. Sets DAC and input
registers to either zero-scale (000
H
) or mid-scale
(800
H
) when LOW. RESETSEL determines which
code is active.
When LOW, a LOW on RESET will cause the DAC
and input registers to be set to code 000
H
. When
RESETSEL is HIGH, a LOW on RESET will set the
registers to code 800
H
.
PIN DESCRIPTIONS—E Package
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
LABEL
V
DD
V
OUTD
V
OUTC
V
REFL
NIC
NIC
V
REFH
V
OUTB
V
OUTA
AGND
GND
SDI
CLK
CS
NIC
NIC
LDAC
DESCRIPTION
Positive Analog Supply Voltage, +3V nominal.
DAC D Voltage Output
DAC C Voltage Output
Reference Input Voltage Low. Sets minimum out-
put voltage for all DACs.
Not Internally Connected.
Not Internally Connected.
Reference Input Voltage High. Sets maximum out-
put voltage for all DACs.
DAC B Voltage Output
DAC A Voltage Output
Analog Ground
Ground
Serial Data Input
Serial Data Clock
Chip Select Input
Not Internally Connected.
Not Internally Connected.
All DAC registers becomes transparent when LDAC
is LOW. They are in the latched state when LDAC
is HIGH.
The selected input register becomes transparent
when LOADREG is LOW. It is in the latched state
when LOADREG is HIGH.
Asynchronous Reset Input. Sets all DAC registers
to either zero-scale (000
H
) or mid-scale (800
H
)
when LOW. RESETSEL determines which code is
active.
When LOW, a LOW on RESET will cause all DAC
registers to be set to code 000
H
. When RESETSEL
is HIGH, a LOW on RESET will set the registers to
code 800
H
.
14
LOADREG
15
RESET
16
RESETSEL
18
LOADREG
19
RESET
20
RESETSEL
4
DAC7617
SBAS185
TYPICAL PERFORMANCE CURVES
At T
A
= +25°C, V
DD
= +3V, V
REFH
= +1.25V, and V
REFL
= 0V, representative unit, unless otherwise specified.
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