DSC510-05
Crystal-less™ Four Output LAN Clock Generator
General Description
The DSC510-05 is a Crystal-less™, four
output clock generator that implements
Discera’s
proven
PureSilicon™
MEMS
technology.
The devices implements
proven silicon MEMS technology to provide
excellent jitter and stability over a wide
range of supply voltages and temperatures.
By eliminating the external quartz crystal,
MEMS
clock
generators
significantly
enhance reliability and accelerate product
development, while meeting stringent clock
performance criteria for a variety of
communications, storage, and networking
applications.
DSC510-05 has an Output Enable / Disable
feature allowing it to disable all outputs
when OE1 and OE2 are low. Each output
enable pin controls one of the two banks of
synchronous clocks. See the OE function
table 1 for more detail.
The device is
available in a 20 pin QFN. Additional output
formats are in any combination of LVPECL,
LVDS, LVCMOS and HCSL.
Features
Four 25MHz LVPECL Clocks
Available Output Formats:
o
o
o
o
o
HCSL, LVPECL, LVCMOS, or LVDS
Mixed Outputs: LVPECL/HCSL/LVDS/CMOS
Ext. Industrial: -40° to 105° C
Industrial: -40° to 85° C
Ext. commercial: -20° to 70° C
Wide Temperature Range
Supply Range of 2.25 to 3.6 V
Low Power Consumption
o
o
o
30% lower than competing devices
Qualified to MIL-STD-883
20 QFN
Excellent Shock & Vibration Immunity
Available Footprints:
Lead Free & RoHS Compliant
Short Lead Time: 2 Weeks
AEC-Q100 Automotive Qualified
Block Diagram
Applications
Communications/Networking
o
o
o
o
o
Ethernet/ LAN PHY
1G, 10GBASE-T/KR/LR/SR, and FcoE
Routers and Switches
Gateways, VoIP, Wireless AP’s
Passive Optical Networks
*
Clk0+/-, Clk1+/-, Clk2 +/- and Clk3 +/- are
25MHz clocks for LAN applications. For other
frequencies, please contact the factory.
_____________________________________________________________________________________________________________________________ _________________
DSC510-05
Page 1
DSC510-05
Crystal-less™ Four Output LAN Clock Generator
Specifications
(Unless specified otherwise: T=25° C,
VDD =3.3V)
Parameter
Supply Voltage
1
Supply Current
Supply Current
2
(Four HCSL Outputs)
V
DD
I
DD
I
DD
EN pin low – outputs are
disabled
EN pin high – outputs are
enabled
R
L
=50 Ω,
All Outputs Running
Includes frequency variations
due to initial tolerance, temp.
and power supply voltage
T=25°C
0.75xV
DD
-
Condition
Min.
2.25
Typ.
42
Max.
3.6
46
Unit
V
mA
120
±100
±50
5
-
0.25xV
DD
5
20
mA
Frequency Stability
Startup Time
3
Input Logic Levels
Input logic high
Input logic low
Output Disable Time
4
Output Enable Time
Pull-Up Resistor
2
Δf
t
SU
V
IH
V
IL
t
DA
t
EN
ppm
ms
V
ns
ns
kΩ
Pull-up on OE pin
40
LVPECL Outputs
Output Logic Levels
Output logic high
Output logic low
Pk to Pk Output Swing
Output Transition time
3
Rise Time
Fall Time
Frequency
Output Duty Cycle
Period Jitter
Integrated Phase Noise
t
R
t
F
f
0
SYM
J
PER
J
PH
200kHz to 20MHz @25MHz
100kHz to 20MHz @25MHz
12kHz to 20MHz @25MHz
V
OH
V
OL
R
L
=50Ω
Single-Ended
20% to 80%
R
L
=50Ω, C
L
= 0pF
Single Frequency
Differential
2.3
48
2.5
0.25
0.38
1.7
V
DD
-1.08
-
800
250
460
52
-
V
DD
-1.55
V
mV
ps
MHz
%
ps
RMS
ps
RMS
2
Notes:
1. Each V
DD
pin should be filtered with 0.01uf capacitor.
2. Output is enabled if OE pin is floated or not connected.
3. t
su
is time to 100PPM stable output frequency after V
DD
is applied and outputs are enabled.
4. Output Waveform and Connection Diagram define the parameters.
5. Period Jitter includes crosstalk from adjacent output.
6. Contact
Sales@Discera.com
for alternate output options (LVPECL, LVDS, LVCMOS).
7. Contact
Sales@Discera.com
for alternative frequency options
8. Jitter limits established by Gen 1.1, Gen 2.1, and Gen 3.0 PCIe standards.
_____________________________________________________________________________________________________________________________ _________________
DSC510-05
Page 2
DSC510-05
Crystal-less™ Four Output LAN Clock Generator
Absolute Maximum Ratings
Item
Supply Voltage
Input Voltage
Junction Temp
Storage Temp
Soldering Temp
ESD
HBM
MM
CDM
Min
-0.3
-0.3
-
-55
-
-
Max
+4.0
V
DD
+0.3
+150
+150
+260
4000
400
1500
Unit
V
V
°C
°C
°C
V
Condition
40sec max.
Solder Reflow Profile
20-40
Sec
Temperature (°C)
217
°
C
200
°
C
.
ax
3C
/
Se
cM
ax
60-150
Sec
260
°
C
.
S
6C/
6C/
6C/
c
c
ec
Ma
Ma
Ma
150
°
C
3C
/
Se
60-180
Sec
cM
Reflow
.
.
x.
Pre heat
8 min max
Cool
Time
25
°
C
20 QFN
MSL 1 @ 260°C refer to JSTD-020C
Ramp-Up Rate (200°C to Peak Temp)
3°C/Sec Max.
Preheat Time 150°C to 200°C
60-180 Sec
Time maintained above 217°C
60-150 Sec
Peak Temperature
255-260°C
Time within 5°C of actual Peak
20-40 Sec
Ramp-Down Rate
6°C/Sec Max.
Time 25°C to Peak Temperature
8 min Max.
_____________________________________________________________________________________________________________________________ _________________
DSC510-05
Page 3
DSC510-05
Crystal-less™ Four Output LAN Clock Generator
Pin Description (20 QFN)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin Name
OE1
NC
VSS
VSS
CLK0-
CLK0+
CLK1-
CLK1+
VDD
NC
OE2
NC
VSS
VSS
CLK2-
CLK2+
CLK3-
CLK3+
VDD
NC
Pin Type
I
NA
Power
Power
O
O
O
O
Power
NA
I
NA
Power
Power
O
O
O
O
Power
NA
Description
Output Enable; active high – See Table 1
Leave unconnected or grounded
Ground
Ground
Complement output of differential pair
True output of differential pair
Complement output of differential pair
True output of differential pair
Power Supply
Leave unconnected or grounded
Output Enable; active high – See Table 1
Leave unconnected or grounded
Ground
Ground
Complement output of differential pair
True output of differential pair
Complement output of differential pair
True output of differential pair
Power Supply
Leave unconnected or grounded
_____________________________________________________________________________________________________________________________ _________________
DSC510-05
Page 4
DSC510-05
Crystal-less™ Four Output LAN Clock Generator
Pin Diagram (20
QFN)
CLK3+
CLK2+
16
CLK3-
20
OE1
NC
VSS
VSS
1
2
3
4
5
19
18
17
15
14
13
12
11
VSS
VSS
NC
OE2
6
7
8
9
10
CLK0+
CLK1+
CLK0-
CLK1-
20 QFN 5.0 x 3.2mm
Connection Diagram (20 QFN Four LVPECL Outputs)
_____________________________________________________________________________________________________________________________ _________________
DSC510-05
Page 5
VDD
NC
CLK2-
VDD
NC
FPGA/CPLD
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