INTEGRATED CIRCUITS
83C748/87C748
80C51 8-bit microcontroller family
2K/64 OTP/ROM, low pin count
Preliminary specification
Supersedes data of 1998 Apr 23
IC20 Data Handbook
1999 Apr 15
Philips
Semiconductors
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, low pin count
83C748/87C748
DESCRIPTION
The Philips 83C748/87C748 offers the advantages of the 80C51
architecture in a small package and at low cost.
The 8XC748 Microcontroller is fabricated with Philips high-density
CMOS technology. Philips epitaxial substrate minimizes CMOS
latch-up sensitivity.
The 8XC748 contains a 2k
×
8 ROM (83C748) EPROM (87C748), a
64
×
8 RAM, 19 I/O lines, a 16-bit auto-reload counter/timer, a
four-source, fixed-priority level interrupt structure, and an on-chip
oscillator.
PIN CONFIGURATIONS
P3.4/A4 1
P3.3/A3 2
P3.2/A2/A10 3
P3.1/A1/A9 4
P3.0/A0/A8 5
P0.2/V
PP
6
P0.1/OE–PGM
7
8
9
PLASTIC
DUAL
IN-LINE
AND
SHRINK
SMALL
OUTLINE
PACKAGE
24 V
CC
23 P3.5/A5
22 P3.6/A6
21 P3.7/A7
20 P1.7/T0/D7
19 P1.6/INT1/D6
18 P1.5/INT0/D5
17 P1.4/D4
16 P1.3/D3
15 P1.2/D2
14 P1.1/D1
13 P1.0/D0
FEATURES
•
80C51 based architecture
•
Small package sizes
–
24-pin DIP (300 mil “skinny DIP”)
–
24-pin Shrink Small Outline Package (SSOP)
–
28-pin PLCC
P0.0/ASEL
RST
X2 10
X1 11
V
SS
12
4
5
PLASTIC
LEADED
CHIP
CARRIER
11
12
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Function
P3.4/A4
P3.3/A3
P3.2/A2/A10
P3.1/A1/A9
NC*
P3.0/A0/A8
P0.2/V
PP
P0.1/OE-PGM
P0.0/ASEL
NC*
RST
X2
X1
V
SS
18
Pin
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1
26
•
87C748 available in erasable quartz lid or one-time programmable
plastic packages
•
Wide oscillator frequency range: –3.5 to 16MHz
•
Low power consumption:
–
Normal operation: less than 11mA @ 5V, 12MHz
–
Idle mode
–
Power-down mode
25
19
•
2k
×
8 ROM (83C748)
2k
×
8 EPROM (87C748)
•
64
×
8 RAM
•
16-bit auto reloadable counter/timer
•
10-bit fixed-rate timer
•
Boolean processor
•
CMOS and TTL compatible
•
Well suited for logic replacement, consumer and industrial
applications
Function
P1.0/D0
P1.1/D1
P1.2/D2
P1.3/D3
P1.4/D4
P1.5/INT0/D5
NC*
NC*
P1.6/INT1/D6
P1.7/T0/D7
P3.7/A7
P3.6/A6
P3.5/A5
V
CC
* NO INTERNAL CONNECTION
SU00295A
•
LED drive outputs
ORDERING INFORMATION
ROM
P83C748EBP N
P83C748EBA A
P83C748EBD DB
EPROM
1
P87C748EBP N
P87C748EBA A
P87C748EBD DB
OTP
OTP
OTP
TEMPERATURE RANGE
°
C
AND PACKAGE
0 to +70, Plastic Dual In-line Package
0 to +70, Plastic Leaded Chip Carrier
0 to +70, Shrink Small Outline Package
FREQUENCY
MHz
3.5 to 16
3.5 to 16
3.5 to 16
DRAWING
NUMBER
SOT222-1
SOT261-3
SOT340-1
NOTE:
1. OTP = One Time Programmable EPROM.
1999 Apr 15
2
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, low pin count
83C748/87C748
BLOCK DIAGRAM
P0.0–P0.2
PORT 0
DRIVERS
V
CC
V
SS
RAM ADDR
REGISTER
RAM
PORT 0
LATCH
ROM/
EPROM
B
REGISTER
ACC
STACK
POINTER
PROGRAM
ADDRESS
REGISTER
TMP2
TMP1
ALU
PCON
IE
TH0
TL0
RTL
RTH
TCON
BUFFER
PSW
INTERRUPT AND
TIMER BLOCKS
PC
INCRE-
MENTER
PROGRAM
COUNTER
INSTRUCTION
REGISTER
RST
TIMING
AND
CONTROL
DPTR
PD
PORT 1
LATCH
PORT 3
LATCH
OSCILLATOR
PORT 1
DRIVERS
X1
X2
P1.0–P1.7
P3.0–P3.7
PORT 3
DRIVERS
SU00296
1999 Apr 15
3
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, low pin count
83C748/87C748
PIN DESCRIPTIONS
PIN NO.
MNEMONIC
V
SS
V
CC
P0.0–P0.2
DIP/
SSOP
12
24
8–6
LCC
14
28
9–7
TYPE
I
I
I/O
Circuit Ground Potential
Supply voltage during normal, idle, and power-down operation.
Port 0:
Port 0 is a 3-bit open-drain, bidirectional port. Port 0 pins that have 1s written to them float,
and in that state can be used as high-impedance inputs. These pins are driven low if the port register
bit is written with a 0. The state of the pin can always be read from the port register by the program.
P0.0 and P0.1 are open drain bidirectional I/O pins. While these differ from “standard TTL”
characteristics, they are close enough for the pins to still be used as general-purpose I/O. Port 0
also provides alternate functions for programming the EPROM memory as follows:
V
PP
(P0.2) –
Programming voltage input. (See Note 1).
OE/PGM (P0.1) –
Input which specifies verify mode (output enable) or the program mode.
OE/PGM = 1 output enabled (verify mode).
OE/PGM = 0 program mode.
ASEL (P0.0) –
Input which indicates which bits of the EPROM address are applied to port 3.
ASEL = 0 low address byte available on port 3.
ASEL = 1 high address byte available on port 3 (only the three least significant bits are used).
Port 1:
Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have 1s written
to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins
that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical
Characteristics: I
IL
). Port 1 serves to output the addressed EPROM contents in the verify mode and
accepts as inputs the value to program into the selected address during the program mode. Port 1
also serves the special function features of the 80C51 family as listed below:
INT0 (P1.5):
External interrupt.
INT1 (P1.6):
External interrupt.
T0 (P1.7):
Timer 0 external input.
Port 3:
Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s written
to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins
that are externally being pulled low will source current because of the pull-ups. (See DC Electrical
Characteristics: I
IL
). Port 3 also functions as the address input for the EPROM memory location to be
programmed (or verified). The 11-bit address is multiplexed into this port as specified by P0.0/ASEL.
Reset:
A high on this pin for two machine cycles while the oscillator is running, resets the device.
An internal diffused resistor to V
SS
permits a power-on RESET using only an external capacitor to
V
CC
. After the device is reset, a 10-bit serial sequence, sent LSB first, applied to RESET, places
the device in the programming state allowing programming address, data and V
PP
to be applied for
programming or verification purposes. The RESET serial sequence must be synchronized with the
X1 input.
Crystal 1:
Input to the inverting oscillator amplifier and input to the internal clock generator circuits.
X1 also serves as the clock to strobe in a serial bit stream into RESET to place the device in the
programming state.
NAME AND FUNCTION
6
7
7
8
N/A
I
8
9
I
P1.0–P1.7
13–20
15–20,
23, 24
I/O
18
19
20
P3.0–P3.7
5–1,
23–21
20
23
24
6, 4–1,
27–25
I
I
I
I/O
RST
9
11
I
X1
11
13
I
X2
10
12
O
Crystal 2:
Output from the inverting oscillator amplifier.
NOTE:
1. When P0.2 is at or close to 0 volts, it may affect the internal ROM operation. It is recommended that P0.2 be tied to V
CC
via a small pull-up
(e.g. 2kW).
ABSOLUTE MAXIMUM RATINGS
1, 2
PARAMETER
Storage temperature range
Voltage from V
CC
to V
SS
Voltage from any pin to V
SS
(except V
PP
)
Power dissipation
Voltage on V
PP
pin to V
SS
Maximum I
OL
per I/O pin
RATING
–65 to +150
–0.5 to +6.5
–0.5 to V
CC
+ 0.5
1.0
0 to +13.0
10
UNIT
°C
V
V
W
V
mA
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
1999 Apr 15
4
Philips Semiconductors
Preliminary specification
80C51 8-bit microcontroller family
2K/64 OTP/ROM, low pin count
83C748/87C748
DC ELECTRICAL CHARACTERISTICS
T
amb
= 0°C to +70°C, V
CC
= 5V
±10%,
V
SS
= 0V
1
SYMBOL
V
IL
V
IH
V
IH1
V
IL1
V
IH2
V
OL
V
OL1
V
OH
PARAMETER
Input low voltage
Input high voltage, except X1, RST
Input high voltage, X1, RST
P0.2
Input low voltage
Input high voltage
Output low voltage, ports 1 and 3
Output low voltage, port 0.2
Output high voltage, ports 1 and 3
I
OL
= 1.6mA
2
I
OL
= 3.2mA
2
I
OH
= –60µA
I
OH
= –25µA
I
OH
= –10µA
I
OL
= 3mA
(over V
CC
range)
V
IN
= 0.45V
V
IN
= 2V (0 to 70°C)
0.45 < V
IN
< V
CC
25
Test freq = 1MHz,
T
amb
= 25°C
V
CC
= 2 to V
CC
max
V
SS
= 0V
V
CC
= 5V±10%
T
amb
= 21°C to 27°C
V
PP
= 13.0V
12.5
2.4
0.75V
CC
0.9V
CC
0.4
10
–50
–650
±10
175
10
50
13.0
50
TEST CONDITIONS
MIN
–0.5
0.2V
CC
+0.9
0.7V
CC
–0.5
0.7V
CC
LIMITS
MAX
0.2V
DD
–0.1
V
CC
+0.5
V
CC
+0.5
0.3V
CC
V
CC
+0.5
0.45
0.45
V
V
V
V
V
V
V
V
V
V
V
pF
µA
µA
µA
kΩ
pF
µA
V
mA
UNIT
V
OL2
C
I
IL
I
TL
I
LI
R
RST
C
IO
I
PD
V
PP
I
PP
I
CC
Port 0.0 and 0.1 – Drivers
Output low voltage
Driver, receiver combined:
Capacitance
Logical 0 input current, ports 1 and 3
Logical 1 to 0 transition current, ports 1 and 3
3
Input leakage current, port 0
Internal pull-down resistor
Pin capacitance
Power-down current
4
V
PP
program voltage (for 87C748 only)
Program current (for 87C748 only)
Supply current (see Figure 2)
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V
SS
unless otherwise
noted.
2. Under steady state (non-transient) conditions, I
OL
must be externally limited as follows:
10mA
Maximum I
OL
per port pin:
Maximum I
OL
per 8-bit port:
26mA
67mA
Maximum total I
OL
for all outputs:
If I
OL
exceeds the test condition, V
OL
may exceed the related specification. Pins are not guaranteed to sink current greater than the listed
test conditions.
3. Pins of ports 1 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its
maximum value when V
IN
is approximately 2V.
4. Power-down I
CC
is measured with all output pins disconnected; port 0 = V
CC
; X2, X1 n.c.; RST = V
SS
.
5. Active I
CC
is measured with all output pins disconnected; X1 driven with t
CLCH
, t
CHCL
= 5ns, V
IL
= V
SS
+ 0.5V, V
IH
= V
CC
– 0.5V; X2 n.c.;
RST = port 0 = V
CC
. I
CC
will be slightly higher if a crystal oscillator is used.
6. Idle I
CC
is measured with all output pins disconnected; X1 driven with t
CLCH
, t
CHCL
= 5ns, V
IL
= V
SS
+ 0.5V, V
IH
= V
CC
– 0.5V; X2 n.c.;
port 0 = V
CC
; RST = V
SS
.
1999 Apr 15
5
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