MC74HC08A
Quad 2-Input AND Gate
High−Performance Silicon−Gate CMOS
The MC74HC08A is identical in pinout to the LS08. The device
inputs are compatible with Standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
Features
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MARKING
DIAGRAMS
14
14
1
SOIC−14
D SUFFIX
CASE 751A
1
14
14
1
TSSOP−14
DT SUFFIX
CASE 948G
1
A
L, WL
Y, YY
W, WW
G or
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
HC
08A
ALYWG
G
HC08AG
AWLYWW
•
•
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1
mA
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7A Requirements
Chip Complexity: 24 FETs or 6 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
•
These Devices are Pb−Free, Halogen Free and are RoHS Compliant
LOGIC DIAGRAM
A1
B1
A2
B2
A3
B3
A4
B4
1
3
2
4
6
5
9
8
10
12
11
13
PIN 14 = V
CC
PIN 7 = GND
Y4
Y3
Y2
Y = AB
Y1
(Note: Microdot may be in either location)
FUNCTION TABLE
Inputs
A
L
L
H
H
B
L
H
L
H
Output
Y
L
L
L
H
Pinout: 14−Lead Packages
(Top View)
V
CC
14
B4
13
A4
12
Y4
11
B3
10
A3
9
Y3
8
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
1
A1
2
B1
3
Y1
4
A2
5
B2
6
Y2
7
GND
©
Semiconductor Components Industries, LLC, 2013
October, 2013
−
Rev. 13
1
Publication Order Number:
MC74HC08A/D
MC74HC08A
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MAXIMUM RATINGS
Symbol
V
CC
V
in
I
in
V
out
I
out
P
D
Parameter
Value
Unit
V
V
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
– 0.5 to + 7.0
– 0.5 to V
CC
+ 0.5
– 0.5 to V
CC
+ 0.5
±
20
±
25
±
50
500
450
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
mA
mA
mA
DC Output Current, per Pin
I
CC
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air,
Storage Temperature
SOIC Package†
TSSOP Package†
mW
_C
_C
T
stg
T
L
– 65 to + 150
260
Lead Temperature, 1 mm from Case for 10 Seconds
SOIC or TSSOP Package
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating — SOIC Package: – 7 mW/_C from 65_ to 125_C
TSSOP Package:
−
6.1 mW/_C from 65_ to 125_C
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND
v
(V
in
or V
out
)
v
V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
RECOMMENDED OPERATING CONDITIONS
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
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Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î
Î
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Î Î Î
Î
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Î Î Î
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Î Î Î
Î
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage
(Referenced to GND)
2.0
0
6.0
V
V
V
in
, V
out
T
A
V
CC
Operating Temperature, All Package Types
Input Rise and Fall Time
(Figure 1)
– 55
0
0
0
+ 125
1000
500
400
_C
ns
t
r
, t
f
V
CC
= 2.0 V
V
CC
= 4.5 V
V
CC
= 6.0 V
Symbol
Parameter
Min
Max
Unit
ORDERING INFORMATION
Device
MC74HC08ADG
MC74HC08ADR2G
MC74HC08ADTR2G
NLV74HC08ADG*
NLV74HC08ADR2G*
NLV74HC08ADTR2G*
Package
Shipping
†
55 Units / Rail
2500 / Tape & Reel
2500 / Tape & Reel
55 Units / Rail
2500 / Tape & Reel
2500 / Tape & Reel
SOIC−14
(Pb−Free)
SOIC−14
(Pb−Free)
TSSOP−14
(Pb−Free)
SOIC−14
(Pb−Free)
SOIC−14
(Pb−Free)
TSSOP−14
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable
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2
MC74HC08A
DC CHARACTERISTICS
(Voltages Referenced to GND)
Symbol
V
IH
Parameter
Minimum High−Level Input Voltage
Condition
V
out
= 0.1V or V
CC
−0.1V
|I
out
|
≤
20mA
V
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
2.0
4.5
6.0
|I
out
|
≤
2.4mA
|I
out
|
≤
4.0mA
|I
out
|
≤
5.2mA
3.0
4.5
6.0
2.0
4.5
6.0
|I
out
|
≤
2.4mA
|I
out
|
≤
4.0mA
|I
out
|
≤
5.2mA
3.0
4.5
6.0
6.0
6.0
Guaranteed Limit
−55
to 25°C
1.50
2.10
3.15
4.20
0.50
0.90
1.35
1.80
1.9
4.4
5.9
2.48
3.98
5.48
0.1
0.1
0.1
0.26
0.26
0.26
±0.1
1.0
≤85°C
1.50
2.10
3.15
4.20
0.50
0.90
1.35
1.80
1.9
4.4
5.9
2.34
3.84
5.34
0.1
0.1
0.1
0.33
0.33
0.33
±1.0
10
≤125°C
1.50
2.10
3.15
4.20
0.50
0.90
1.35
1.80
1.9
4.4
5.9
2.20
3.70
5.20
0.1
0.1
0.1
0.40
0.40
0.40
±1.0
40
mA
mA
V
Unit
V
V
IL
Maximum Low−Level Input Voltage
V
out
= 0.1V or V
CC
−
0.1V
|I
out
|
≤
20mA
V
V
OH
Minimum High−Level Output Voltage
V
in
= V
IH
or V
IL
|I
out
|
≤
20mA
V
in
=V
IH
or V
IL
V
V
OL
Maximum Low−Level Output Voltage
V
in
= V
IH
or V
IL
|I
out
|
≤
20mA
V
in
= V
IH
or V
IL
I
in
I
CC
Maximum Input Leakage Current
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
V
in
= V
CC
or GND
I
out
= 0mA
AC CHARACTERISTICS
(C
L
= 50pF, Input t
r
= t
f
= 6ns)
Symbol
t
PLH
,
t
PHL
Parameter
Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)
V
CC
V
2.0
3.0
4.5
6.0
2.0
3.0
4.5
6.0
Guaranteed Limit
−55
to 25°C
75
30
15
13
75
27
15
13
10
≤85°C
95
40
19
16
95
32
19
16
10
≤125°C
110
55
22
19
110
36
22
19
10
Unit
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
ns
C
in
Maximum Input Capacitance
pF
Typical @ 25°C, V
CC
= 5.0 V, V
EE
= 0 V
C
PD
Power Dissipation Capacitance (Per Buffer)*
20
pF
* Used to determine the no−load dynamic power consumption: P
D
= C
PD
V
CC 2
f + I
CC
V
CC
.
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3
MC74HC08A
t
r
90%
INPUT
A OR B
t
PLH
90%
OUTPUT Y
50%
10%
t
TLH
t
THL
50%
10%
t
PHL
t
f
V
CC
GND
Figure 1. Switching Waveforms
TEST
POINT
OUTPUT
DEVICE
UNDER
TEST
C
L
*
*Includes all probe and jig capacitance
Figure 2. Test Circuit
A
B
Y
Figure 3. Expanded Logic Diagram
(1/4 of the Device)
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4
MC74HC08A
PACKAGE DIMENSIONS
SOIC−14 NB
CASE 751A−03
ISSUE K
D
14
8
A
B
A3
E
L
H
1
7
DETAIL A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
DIM
A
A1
A3
b
D
E
e
H
h
L
M
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0
_
7
_
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0
_
7
_
0.25
M
B
M
13X
b
0.25
M
C A
A
S
B
S
X 45
_
h
DETAIL A
e
A1
C
M
SEATING
PLANE
SOLDERING FOOTPRINT*
6.50
1
14X
1.18
1.27
PITCH
0.58
14X
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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5
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