178-Ball Mobile LPDDR3 SDRAM
Features
Mobile LPDDR3 SDRAM
EDF8132A1MC, EDFA232A1MA
Features
• Ultra-low-voltage core and I/O power supplies
• Frequency range
– 800 MHz (data rate: 1600 Mb/s/pin)
• 8n prefetch DDR architecture
• 8 internal banks for concurrent operation
• Multiplexed, double data rate, command/address
inputs; commands entered on each CK_t/CK_c
edge
• Bidirectional/differential data strobe per byte of
data (DQS_t/DQS_c)
• Programmable READ and WRITE latencies (RL/WL)
• Burst length: 8
• Per-bank refresh for concurrent operation
• Auto temperature-compensated self refresh
(ATCSR) by built-in temperature sensor
• Partial-array self refresh (PASR)
• Deep power-down mode (DPD)
• Selectable output drive strength (DS)
• Clock-stop capability
• On-die termination (ODT)
• Lead-free (RoHS-compliant) and halogen-free
packaging
Options
• V
DD1
/V
DD2
/V
DDCA
/V
DDQ
: 1.8V/1.2V/1.2V/1.2V
• Array configuration
– 256 Meg x 32 (DDP)
– 512 Meg x 32 (QDP)
• Packaging
– 12.0mm x 11.5mm, 178-ball FBGA package
– 13.0mm x 11.5mm, 178-ball FBGA package
• Operating temperature range
– From –30°C to +85°C
Table 1: Configuration Addressing – Single-Channel Package
Architecture
Density per package
Die per package
Ranks (CS_n) per channel
Die per rank
Configuration per rank (CS_n)
Row addressing
Column
addressing/CS_n
CS0_n
CS1_n
CS0_n
CS1_n
CS0_n
CS1_n
256 Meg x 32
8Gb
2
2
1
1
16 Meg x 32 x 8 banks
16 Meg x 32 x 8 banks
16K A[13:0]
1K A[9:0]
1K A[9:0]
512 Meg x 32
16Gb
4
2
2
2
32 Meg x 16 x 8 banks x 2
32 Meg x 16 x 8 banks x 2
16K A[13:0]
2K A[10:0]
2K A[10:0]
PDF: 09005aef858e9dd3
178b_30nm_mobile_lpddr3.pdf – Rev. A 3/14 EN
1
Products and specifications discussed herein are subject to change by Micron without notice.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2014 Micron Technology, Inc. All rights reserved.
178-Ball Mobile LPDDR3 SDRAM
Features
Table 2: Key Timing Parameters
Speed
Grade
GD
Clock Rate
(MHz)
800
Data Rate
(Mb/s/pin)
1600
WRITE Latency
(Set A)
6
READ
Latency
12
Table 3: Part Number Description
Part
Number
EDF8132A1MC-GD-F-D
EDF8132A1MC-GD-F-R
EDFA232A1MA-GD-F-D
EDFA232A1MA-GD-F-R
Total
Density
8Gb
16Gb
Configuration
256 Meg x 32
512 Meg x 32
Ranks
2
2
Channels
1
1
Package
Size
12.0mm x 11.5mm
(0.9mm MAX height)
13.0mm x 11.5mm
(1.1mm MAX height)
Ball
Pitch
0.80mm
0.65mm
0.80mm
0.65mm
Figure 1: Marketing Part Number Chart
E
Micron Technology
(Micron Japan)
Type
D = Packaged device
D
F
81 32
A
1
MC- GD - F - D
Packing Media
D = Dry Pack (Tray)
R = Tape and Reel
Environment Code
F = Lead-free (RoHS-compliant)
and halogen-free
Product Family
F = Mobile LPDDR3 SDRAM
Density/Chip Select
81 = 8Gb/2-CS
A2 = 16Gb/2-CS
Speed
GD = 1600 Mbps
Package
MC = Stacked FBGA
MA = Stacked FBGA
Organization
32 = x32
Power Supply Interface
A = V
DD1
= 1.8V, V
DD2
= V
DDCA
= V
DDQ
= 1.2V,
S8 device, HSUL_12
Revision
Note:
1. The characters highlighted in gray indicate the physical part marking found on the device.
PDF: 09005aef858e9dd3
178b_30nm_mobile_lpddr3.pdf – Rev. A 3/14 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2014 Micron Technology, Inc. All rights reserved.
178-Ball Mobile LPDDR3 SDRAM
Features
Contents
General Description .......................................................................................................................................
Ball Assignments ............................................................................................................................................
Ball Descriptions ............................................................................................................................................
Package Block Diagrams .................................................................................................................................
Package Dimensions .......................................................................................................................................
178-Ball Package – MR0–MR3, MR5–MR8, MR11 Contents ...............................................................................
I
DD
Specifications – Dual Die, Single Channel ..................................................................................................
I
DD
Specifications – Quad Die, Single Channel .................................................................................................
Pin Capacitance .............................................................................................................................................
LPDDR3 Array Configuration ..........................................................................................................................
General Notes ............................................................................................................................................
Functional Description ...................................................................................................................................
Simplified Bus Interface State Diagram ............................................................................................................
Power-Up and Initialization ............................................................................................................................
Voltage Ramp and Device Initialization .......................................................................................................
Initialization After Reset (Without Voltage Ramp) ........................................................................................
Power-Off Sequence .......................................................................................................................................
Uncontrolled Power-Off Sequence ..............................................................................................................
Standard Mode Register Definition ..................................................................................................................
Mode Register Assignments and Definitions ................................................................................................
Commands and Timing ..................................................................................................................................
ACTIVATE Command .....................................................................................................................................
8-Bank Device Operation ............................................................................................................................
Read and Write Access Modes .........................................................................................................................
Burst READ Command ...................................................................................................................................
t
DQSCK Delta Timing .................................................................................................................................
Burst WRITE Command ..................................................................................................................................
Write Data Mask .............................................................................................................................................
PRECHARGE Command .................................................................................................................................
Burst READ Operation Followed by PRECHARGE .........................................................................................
Burst WRITE Followed by PRECHARGE .......................................................................................................
Auto Precharge ...........................................................................................................................................
Burst READ with Auto Precharge .................................................................................................................
Burst WRITE with Auto Precharge ...............................................................................................................
REFRESH Command ......................................................................................................................................
REFRESH Requirements .............................................................................................................................
SELF REFRESH Operation ...............................................................................................................................
Partial-Array Self Refresh (PASR) – Bank Masking .........................................................................................
Partial-Array Self Refresh – Segment Masking ..............................................................................................
MODE REGISTER READ .................................................................................................................................
MRR Following Idle Power-Down State ........................................................................................................
Temperature Sensor ...................................................................................................................................
DQ Calibration ...........................................................................................................................................
MODE REGISTER WRITE ................................................................................................................................
MRW RESET Command ..............................................................................................................................
MRW ZQ Calibration Commands ................................................................................................................
ZQ External Resistor Value, Tolerance, and Capacitive Loading .....................................................................
MRW – CA Training Mode ...........................................................................................................................
MRW - Write Leveling Mode ........................................................................................................................
On-Die Termination (ODT) .............................................................................................................................
10
11
13
14
16
18
20
24
28
29
29
30
32
34
34
36
37
37
38
38
47
48
48
49
50
52
56
60
61
62
63
64
64
65
67
70
72
73
73
75
76
77
78
80
80
81
84
84
86
88
PDF: 09005aef858e9dd3
178b_30nm_mobile_lpddr3.pdf – Rev. A 3/14 EN
3
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2014 Micron Technology, Inc. All rights reserved.
178-Ball Mobile LPDDR3 SDRAM
Features
ODT Mode Register .................................................................................................................................... 88
Asychronous ODT ...................................................................................................................................... 88
ODT During READ Operations (READ or MRR) ............................................................................................ 89
ODT During Power-Down ........................................................................................................................... 89
ODT During Self Refresh ............................................................................................................................. 89
ODT During Deep Power-Down .................................................................................................................. 89
ODT During CA Training and Write Leveling ................................................................................................ 89
Power-Down .................................................................................................................................................. 92
Deep Power-Down ......................................................................................................................................... 98
Input Clock Frequency Changes and Stop Events ............................................................................................. 99
Input Clock Frequency Changes and Clock Stop with CKE LOW ................................................................... 99
Input Clock Frequency Changes and Clock Stop with CKE HIGH ................................................................. 100
NO OPERATION Command ........................................................................................................................... 100
Truth Tables .................................................................................................................................................. 101
Absolute Maximum Ratings ........................................................................................................................... 108
Electrical Specifications – I
DD
Measurements and Conditions ......................................................................... 109
I
DD
Specifications ...................................................................................................................................... 110
AC and DC Operating Conditions ................................................................................................................... 113
AC and DC Logic Input Measurement Levels for Single-Ended Signals ............................................................. 114
V
REF
Tolerances ......................................................................................................................................... 115
Input Signal .............................................................................................................................................. 116
AC and DC Logic Input Measurement Levels for Differential Signals ................................................................ 118
Single-Ended Requirements for Differential Signals .................................................................................... 119
Differential Input Crosspoint Voltage ......................................................................................................... 120
Input Slew Rate ......................................................................................................................................... 122
Output Characteristics and Operating Conditions ........................................................................................... 123
Single-Ended Output Slew Rate .................................................................................................................. 123
Differential Output Slew Rate ..................................................................................................................... 125
HSUL_12 Driver Output Timing Reference Load ......................................................................................... 127
Output Driver Impedance .............................................................................................................................. 128
Output Driver Impedance Characteristics with ZQ Calibration .................................................................... 129
Output Driver Temperature and Voltage Sensitivity ..................................................................................... 129
Output Impedance Characteristics Without ZQ Calibration ......................................................................... 130
ODT Levels and I-V Characteristics ............................................................................................................ 134
Clock Specification ........................................................................................................................................ 135
t
CK(abs),
t
CH(abs), and
t
CL(abs) ................................................................................................................ 136
Clock Period Jitter .......................................................................................................................................... 136
Clock Period Jitter Effects on Core Timing Parameters ................................................................................. 136
Cycle Time Derating for Core Timing Parameters ........................................................................................ 137
Clock Cycle Derating for Core Timing Parameters ....................................................................................... 137
Clock Jitter Effects on Command/Address Timing Parameters ..................................................................... 137
Clock Jitter Effects on Read Timing Parameters ........................................................................................... 137
Clock Jitter Effects on Write Timing Parameters .......................................................................................... 138
Refresh Requirements .................................................................................................................................... 139
AC Timing ..................................................................................................................................................... 140
CA and CS_n Setup, Hold, and Derating .......................................................................................................... 147
Data Setup, Hold, and Slew Rate Derating ....................................................................................................... 154
Revision History ............................................................................................................................................ 161
Rev. A – 03/14 ............................................................................................................................................ 161
PDF: 09005aef858e9dd3
178b_30nm_mobile_lpddr3.pdf – Rev. A 3/14 EN
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2014 Micron Technology, Inc. All rights reserved.
178-Ball Mobile LPDDR3 SDRAM
Features
List of Figures
Figure 1: Marketing Part Number Chart ............................................................................................................ 2
Figure 2: 178-Ball Single-Channel FBGA – 2 x 4Gb Die, 12.0mm x 11.5mm ....................................................... 11
Figure 3: 178-Ball Single-Channel FBGA – 4 x 4Gb Die, 13.0mm x 11.5mm ....................................................... 12
Figure 4: Dual-Rank, Dual-Die, Single-Channel Package Block Diagram .......................................................... 14
Figure 5: Dual-Rank, Quad-Die, Single-Channel Package Block Diagram ......................................................... 15
Figure 6: 178-Ball FBGA (12.0mm x 11.5mm) – EDF8132A1MC ........................................................................ 16
Figure 7: 178-Ball FBGA (13.0mm x 11.5mm) – EDFA232A1MA ........................................................................ 17
Figure 8: Functional Block Diagram ............................................................................................................... 31
Figure 9: Simplified State Diagram ................................................................................................................. 33
Figure 10: Voltage Ramp and Initialization Sequence ...................................................................................... 36
Figure 11: Command and Input Setup and Hold ............................................................................................. 47
Figure 12: CKE Input Setup and Hold ............................................................................................................. 47
Figure 13: ACTIVATE Command .................................................................................................................... 48
Figure 14:
t
FAW Timing .................................................................................................................................. 49
Figure 15: READ Output Timing ..................................................................................................................... 50
Figure 16: Burst READ – RL = 12, BL = 8,
t
DQSCK >
t
CK ................................................................................... 50
Figure 17: Burst READ – RL = 12, BL = 8,
t
DQSCK <
t
CK ................................................................................... 51
Figure 18: Burst READ Followed by Burst WRITE – RL = 12, WL = 6, BL = 8 ....................................................... 51
Figure 19: Seamless Burst READ – RL = 6, BL = 8,
t
CCD = 4 .............................................................................. 52
Figure 20:
t
DQSCKDL Timing ........................................................................................................................ 53
Figure 21:
t
DQSCKDM Timing ....................................................................................................................... 54
Figure 22:
t
DQSCKDS Timing ......................................................................................................................... 55
Figure 23: Data Input (WRITE) Timing ........................................................................................................... 56
Figure 24: Burst WRITE ................................................................................................................................. 57
Figure 25: Method for Calculating
t
WPRE Transitions and Endpoints ............................................................... 57
Figure 26: Method for Calculating
t
WPST Transitions and Endpoints ............................................................... 58
Figure 27: Burst WRITE Followed by Burst READ ............................................................................................ 58
Figure 28: Seamless Burst WRITE – WL = 4, BL = 8,
t
CCD = 4 ............................................................................ 59
Figure 29: Data Mask Timing ......................................................................................................................... 60
Figure 30: Write Data Mask – Second Data Bit Masked .................................................................................... 60
Figure 31: Burst READ Followed by PRECHARGE – BL = 8, RU(
t
RTP(MIN)/
t
CK) = 2 ........................................... 62
Figure 32: Burst WRITE Followed by PRECHARGE – BL = 8 .............................................................................. 63
Figure 33: LPDDR3 – Burst READ with Auto Precharge .................................................................................... 64
Figure 34: Burst WRITE with Auto Precharge – BL = 8 ...................................................................................... 65
Figure 35: REFRESH Command Timing .......................................................................................................... 69
Figure 36: Postponing REFRESH Commands .................................................................................................. 69
Figure 37: Pulling In REFRESH Commands .................................................................................................... 69
Figure 38: All-Bank REFRESH Operation ........................................................................................................ 71
Figure 39: Per-Bank REFRESH Operation ....................................................................................................... 71
Figure 40: SELF REFRESH Operation .............................................................................................................. 73
Figure 41: MRR Timing .................................................................................................................................. 75
Figure 42: READ to MRR Timing .................................................................................................................... 76
Figure 43: Burst WRITE Followed by MRR ...................................................................................................... 76
Figure 44: MRR After Idle Power-Down Exit .................................................................................................... 77
Figure 45: Temperature Sensor Timing ........................................................................................................... 78
Figure 46: MR32 and MR40 DQ Calibration Timing ......................................................................................... 79
Figure 47: MODE REGISTER WRITE Timing ................................................................................................... 80
Figure 48: MODE REGISTER WRITE Timing for MRW RESET .......................................................................... 81
Figure 49: ZQ Timings ................................................................................................................................... 83
Figure 50: CA Training Timing ....................................................................................................................... 84
PDF: 09005aef858e9dd3
178b_30nm_mobile_lpddr3.pdf – Rev. A 3/14 EN
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
©
2014 Micron Technology, Inc. All rights reserved.
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