Temperature range is as follows: A and B Versions: –40°C to +85°C.
2
Common-mode voltage. The input signal can be centered on any choice of dc common-mode voltage as long as this value is in the range specified in Figures 8 and 9.
3
See Terminology section.
4
A 200 mV p-p sine wave, varying in frequency from 1 kHz to 200 kHz is coupled onto V
DD
. A 2.2 nF capacitor is used to decouple V
DD
to GND.
5
If the input spans of V
IN+
and V
IN–
are both V
REF
, and they are 180° out of phase, the differential voltage is 2 V
REF
.
6
The AD7450 is functional with a reference input from 100 mV and for V
DD
= 5 V, the reference can range up to 3.5 V (see References section).
7
The AD7450 is functional with a reference input from 100 mV and for V
DD
= 3 V, the reference can range up to 2.2 V (see References section).
8
Sample tested @ 25°C to ensure compliance.
9
See Serial Interface section.
10
See Power Versus Throughput Rate section.
11
Measured with a midscale dc input.
REV. 0
–3–
AD7450
TIMING SPECIFICATIONS
1, 2
f
SCLK
= 18 MHz, f
S
= 1 MSPS, V
REF
= 2.5 V; V
CM
Limit at T
MIN
, T
MAX
3V
5V
50
15
16 t
SCLK
1.07
25
10
10
20
40
0.4 t
SCLK
0.4 t
SCLK
10
10
35
1
50
18
16 t
SCLK
0.88
25
10
10
20
40
0.4 t
SCLK
0.4 t
SCLK
10
10
35
1
Parameter
f
SCLK4
t
CONVERT
t
QUIET
t
1
t
2
t
3 5
t
4 5
t
5
t
6
t
7
t
8 6
t
POWER-UP7
3
(V
DD
= 2.7 V to 3.3 V, f
SCLK
= 15 MHz, f
S
= 833 kSPS, V
REF
= 1.25 V; V
DD
= 4.75 V to 5.25 V,
= V
REF
; T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Unit
kHz min
MHz max
µs
max
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
µs
max
Description
t
SCLK
= 1/f
SCLK
SCLK = 15 MHz, 18 MHz
Minimum Quiet Time between the End of a Serial Read and the Next
Falling Edge of
CS
Minimum
CS
Pulsewidth
CS
Falling Edge to SCLK Falling Edge Setup Time
Delay from
CS
Falling Edge until SDATA Three-State Disabled
Data Access Time after SCLK Falling Edge
SCLK High Pulsewidth
SCLK Low Pulsewidth
SCLK Edge to Data Valid Hold Time
SCLK Falling Edge to SDATA Three-State Enabled
SCLK Falling Edge to SDATA Three-State Enabled
Power-Up Time from Full Power-Down
NOTES
1
Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD
) and timed from a voltage level of 1.6 V.
2
See Figure 1 and the Serial Interface section.
3
Common-mode voltage.
4
Mark/space ratio for the SCLK input is 40/60 to 60/40.
5
Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V with V
DD
= 5 V, and the time for an output to cross
0.4 V or 2.0 V for V
DD
= 3 V.
6
t
8
is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t
8
, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
7
See Power-Up Time section.
Specifications subject to change without notice.
t
1
CS
t
CONVERT
t
2
SCLK
1
2
3
4
5
13
14
15
16
t
5
t
7
t
3
SDATA
0
0
0
0
t
6
t
8
t
QUIET
t
4
DB11
DB10
DB2
DB1
DB0
THREE-STATE
4 LEADING ZEROS
Figure 1. Serial Interface Timing Diagram
–4–
REV. 0
AD7450
ABSOLUTE MAXIMUM RATINGS
1
(T
A
= 25°C, unless otherwise noted.)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
V
IN+
to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
V
IN–
to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Input Voltage to GND . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Digital Output Voltage to GND . . . . . –0.3 V to V
DD
+ 0.3 V
V
REF
to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to V
DD
+ 0.3 V
Input Current to Any Pin Except Supplies
2
. . . . . . .
±
10 mA
Operating Temperature Range
Commercial (A and B Version) . . . . . . . . . –40
o
C to +85
o
C
Storage Temperature Range . . . . . . . . . . . . –65
PCB设计
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