All operations (Reads, Writes, and Deselects) are pipe lined.
ADV/LD must be driven LOW after the device has been
deselected to load a new address for the next operation.
Single Read Accesses
A read access is initiated when the following conditions are
satisfied at clock rise: (1) CEN is asserted LOW, (2) CE
1
, CE
2
,
and CE
3
are ALL asserted active, (3) the Write Enable input
signal WE is deasserted HIGH, and 4) ADV/LD is asserted
LOW. The address presented to the address inputs is latched
into the Address Register and presented to the memory array
and control logic. The control logic determines that a read
access is in progress and allows the requested data to
propagate to the output buffers. The data is available within 6.5
ns (133-MHz device) provided OE is active LOW. After the first
clock of the read access, the output buffers are controlled by
OE and the internal control logic. OE must be driven LOW in
order for the device to drive out the requested data. On the
subsequent clock, another operation (Read/Write/Deselect)
can be initiated. When the SRAM is deselected at clock rise
by one of the chip enable signals, its output is tri-stated
immediately.
Burst Read Accesses
The CY7C1353G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Reads without reasserting the address inputs. ADV/LD
must be driven LOW to load a new address into the SRAM, as
described in the Single Read Access section. The sequence
of the burst counter is determined by the MODE input signal.
A LOW input on MODE selects a linear burst mode, a HIGH
selects an interleaved burst sequence. Both burst counters
use A0 and A1 in the burst sequence, and wraps around when
incremented sufficiently. A HIGH input on ADV/LD increments
the internal burst counter regardless of the state of chip enable
inputs or WE. WE is latched at the beginning of a burst cycle.
Therefore, the type of access (Read or Write) is maintained
throughout the burst sequence.
Single Write Accesses
Write access are initiated when these conditions are satisfied
at clock rise:
• CEN is asserted LOW
• CE
1
, CE
2
, and CE
3
are ALL asserted active
• The write signal WE is asserted LOW.
The address presented to the address bus is loaded into the
Address Register. The write signals are latched into the
Control Logic block. The data lines are automatically tri-stated
regardless of the state of the OE input signal. This allows the
external logic to present the data on DQs and DQP
[A:B]
.
On the next clock rise the data presented to DQs and DQP
[A:B]
(or a subset for byte write operations, see truth table for
details) inputs is latched into the device and the write is
complete. Additional accesses (Read/Write/Deselect) can be
initiated on this cycle.
The data written during the Write operation is controlled by
BW
[A:B]
signals. The CY7C1353G provides byte write
capability that is described in the truth table. Asserting the
Write Enable input (WE) with the selected Byte Write Select
input selectively writes to only the desired bytes. Bytes not
selected during a byte write operation remains unaltered. A
synchronous self timed write mechanism has been provided
to simplify the write operations. Byte write capability has been
included to greatly simplify Read/Modify/Write sequences,
which can be reduced to simple byte write operations.
Because the CY7C1353G is a common IO device, data must
not be driven into the device while the outputs are active. The
Output Enable (OE) can be deasserted HIGH before
presenting data to the DQs and DQP
[A:B]
inputs. Doing so
tri-states the output drivers. As a safety precaution, DQs and
DQP
[A:B]
.are automatically tri-stated during the data portion of
a write cycle, regardless of the state of OE.
Burst Write Accesses
The CY7C1353G has an on-chip burst counter that allows the
user the ability to supply a single address and conduct up to
four Write operations without reasserting the address inputs.
ADV/LD must be driven LOW to load the initial address, as
described in the Single Write Access section. When ADV/LD
is driven HIGH on the subsequent clock rise, the Chip Enables
(CE
1
, CE
2
, and CE
3
) and WE inputs are ignored and the burst
counter is incremented. The correct BW
[A:B]
inputs must be
driven in each cycle of the burst write, to write the correct bytes
of data.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE
1
, CE
2
, and CE
3
, must remain inactive
for the duration of t
ZZREC
after the ZZ input returns LOW.
Document #: 38-05515 Rev. *E
Page 4 of 13
[+] Feedback
CY7C1353G
Linear Burst Address Table (MODE = GND)
First
Address
A1, A0
00
01
10
11
Second
Address
A1, A0
01
10
11
00
Third
Address
A1, A0
10
11
00
01
Fourth
Address
A1, A0
11
00
01
10
Interleaved Burst Address Table
(MODE = Floating or V
DD
)
First
Address
A1, A0
00
01
10
11
Second
Address
A1, A0
01
00
11
10
Third
Address
A1, A0
10
11
00
01
Fourth
Address
A1, A0
11
10
01
00
ZZ Mode Electrical Characteristics
Parameter
I
DDZZ
t
ZZS
t
ZZREC
t
ZZI
t
RZZI
Description
Sleep mode standby current
Device operation to ZZ
ZZ recovery time
ZZ active to sleep current
ZZ inactive to exit sleep current
Test Conditions
ZZ > V
DD
−
0.2V
ZZ > V
DD
−
0.2V
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
0
2t
CYC
2t
CYC
Min
Max
40
2t
CYC
Unit
mA
ns
ns
ns
ns
Truth Table
[2, 3, 4, 5, 6, 7, 8]
Operation
Deselect Cycle
Deselect Cycle
Deselect Cycle
Continue Deselect Cycle
READ Cycle (Begin Burst)
READ Cycle (Continue Burst)
NOP/DUMMY READ (Begin
Burst)
DUMMY READ (Continue Burst)
WRITE Cycle (Begin Burst)
WRITE Cycle (Continue Burst)
NOP/WRITE ABORT (Begin
Burst)
WRITE ABORT (Continue Burst)
IGNORE CLOCK EDGE (Stall)
SLEEP MODE
Address
Used
None
None
None
None
External
Next
External
Next
External
Next
None
Next
Current
None
CE
1
H
X
X
X
L
X
L
X
L
X
L
X
X
X
CE
2
X
X
L
X
H
X
H
X
H
X
H
X
X
X
CE
3
X
H
X
X
L
X
L
X
L
X
L
X
X
X
ZZ
L
L
L
L
L
L
L
L
L
L
L
L
L
H
ADV/LD
L
L
L
H
L
H
L
H
L
H
L
H
X
X
WE
X
X
X
X
H
X
H
X
L
X
L
X
X
X
BW
X
OE
X
X
X
X
X
X
X
X
L
L
H
H
X
X
X
X
X
X
L
L
H
H
X
X
X
X
X
X
CEN
L
L
L
L
L
L
L
L
L
L
L
L
H
X
CLK
L->H
L->H
L->H
L->H
DQ
Tri-State
Tri-State
Tri-State
Tri-State
L->H Data Out (Q)
L->H Data Out (Q)
L->H
L->H
Tri-State
Tri-State
L->H Data In (D)
L->H Data In (D)
L->H
L->H
L->H
X
Tri-State
Tri-State
–
Tri-State
Notes:
2. X =”Don't Care.” H = Logic HIGH, L = Logic LOW. BWx = L signifies at least one Byte Write Select is active, BWx = Valid signifies that the desired byte write
selects are asserted, see truth table for details.
3. Write is defined by BW
X
, and WE. See truth table for Read/Write.
4. When a write cycle is detected, all IOs are tri-stated, even during byte writes.
5. The DQs and DQP
[A:B]
pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
6. CEN = H, inserts wait states.
7. Device powers up deselected and the IOs in a tri-state condition, regardless of OE.
8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle DQs and DQP
[A:B]
= tri-state when OE
is inactive or when the device is deselected, and DQs and DQP
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