CY7C1347G
4-Mbit (128K x 36) Pipelined Sync SRAM
Features
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Functional Description
[1]
The CY7C1347G is a 3.3V, 128K x 36 synchronous-pipelined
SRAM designed to support zero-wait-state secondary cache
with minimal glue logic. CY7C1347G IO pins can operate at
either the 2.5V or the 3.3V level. The IO pins are 3.3V tolerant
when V
DDQ
= 2.5V. All synchronous inputs pass through input
registers controlled by the rising edge of the clock. All data
outputs pass through output registers controlled by the rising
edge of the clock. Maximum access delay from the clock rise is
2.6 ns (250 MHz device). CY7C1347G supports either the
interleaved burst sequence used by the Intel Pentium processor
or a linear burst sequence used by processors such as the
PowerPC
®
. The burst sequence is selected through the MODE
pin. Accesses can be initiated by asserting either the Address
Strobe from Processor (ADSP) or the Address Strobe from
Controller (ADSC) at clock rise. Address advancement through
the burst sequence is controlled by the ADV input. A 2-bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the rest
of the burst access.
Byte write operations are qualified with the four Byte Write Select
(BW
[A:D]
) inputs. A Global Write Enable (GW) overrides all byte
write inputs and writes data to all four bytes. All writes are
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Selects (CE
1
, CE
2
, CE
3
) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. To provide proper data
during depth expansion, OE is masked during the first clock of a
read cycle when emerging from a deselected state.
Fully registered inputs and outputs for pipelined operation
128K x 36 common IO architecture
3.3V core power supply (V
DD
)
2.5V/3.3V IO power supply (V
DDQ
)
Fast clock to output times: 2.6 ns (for 250 MHz device)
User-selectable burst counter supporting Intel
®
Pentium
®
interleaved or linear burst sequences
Separate processor and controller address strobes
Synchronous self-timed writes
Asynchronous output enable
Offered in Pb-free 100-Pin TQFP, Pb-free and non Pb-free
119-Ball BGA package, and 165-Ball FBGA package
“ZZ” sleep mode option and stop clock option
Available in industrial and commercial temperature ranges
Selection Guide
Specification
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
250 MHz
2.6
325
40
200 MHz
2.8
265
40
166 MHz
3.5
240
40
133 MHz
4.0
225
40
Unit
ns
mA
mA
Note
1. For best practice recommendations, refer to the Cypress application note
AN1064, SRAM System Guidelines.
Cypress Semiconductor Corporation
Document #: 38-05516 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised January 15, 2009
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CY7C1347G
Block Diagram
A0, A1, A
ADDRESS
REGISTER
2
A
[1:0]
MODE
ADV
CLK
Q1
ADSC
ADSP
BW
D
DQ
D ,
DQP
D
BYTE
WRITE REGISTER
DQ
C ,
DQP
C
BYTE
WRITE REGISTER
DQ
B ,
DQP
B
BYTE
WRITE REGISTER
DQ
A ,
DQP
A
BYTE
WRITE REGISTER
BURST
COUNTER
CLR
AND
LOGIC
Q0
DQ
D
,DQP
D
BYTE
WRITE DRIVER
DQ
C ,
DQP
C
BYTE
WRITE DRIVER
DQ
B ,
DQP
B
BYTE
WRITE DRIVER
DQ
A ,
DQP
A
BYTE
WRITE DRIVER
BW
C
MEMORY
ARRAY
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
BW
B
DQs
DQP
A
DQP
B
DQP
C
DQP
D
BW
A
BWE
GW
CE
1
CE
2
CE
3
OE
ENABLE
REGISTER
PIPELINED
ENABLE
INPUT
REGISTERS
ZZ
SLEEP
CONTROL
Document #: 38-05516 Rev. *F
Page 2 of 22
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CY7C1347G
Pinouts
Figure 1. 100-Pin TQFP
A
A
CE
1
CE
2
BW
D
BW
C
BW
B
BW
A
CE
3
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
DQP
C
DQ
C
DQ
C
V
DDQ
V
SSQ
DQ
C
DQ
C
DQ
C
DQ
C
V
SSQ
V
DDQ
DQ
C
DQ
C
NC
V
DD
NC
V
SS
DQ
D
DQ
D
V
DDQ
V
SSQ
DQ
D
DQ
D
DQ
D
DQ
D
V
SSQ
V
DDQ
DQ
D
DQ
D
DQP
D
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
BYTE C
BYTE D
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1347G
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQP
B
DQ
B
DQ
B
V
DDQ
V
SSQ
DQ
B
DQ
B
DQ
B
DQ
B
V
SSQ
V
DDQ
DQ
B
DQ
B
V
SS
NC
V
DD
ZZ
DQ
A
DQ
A
V
DDQ
V
SSQ
DQ
A
DQ
A
DQ
A
DQ
A
V
SSQ
V
DDQ
DQ
A
DQ
A
DQP
A
BYTE B
BYTE A
Document #: 38-05516 Rev. *F
MODE
A
A
A
A
A
1
A
0
NC/72M
NC/36M
V
SS
V
DD
NC/18M
NC/9M
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
Page 3 of 22
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CY7C1347G
Pinouts
(continued)
Figure 2. 119-Ball BGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
DDQ
NC/288M
NC/144M
DQ
C
DQ
C
V
DDQ
DQ
C
DQ
C
V
DDQ
DQ
D
DQ
D
V
DDQ
DQ
D
DQ
D
NC
NC
V
DDQ
2
A
CE
2
A
DQP
C
DQ
C
DQ
C
DQ
C
DQ
C
V
DD
DQ
D
DQ
D
DQ
D
DQ
D
DQP
D
A
NC/72M
NC
3
A
A
A
V
SS
V
SS
V
SS
BW
C
V
SS
NC
V
SS
BW
D
V
SS
V
SS
V
SS
MODE
A
NC
4
ADSP
ADSC
V
DD
NC
CE
1
OE
ADV
GW
V
DD
CLK
NC
BWE
A1
A0
V
DD
A
NC
5
A
A
A
V
SS
V
SS
V
SS
BW
B
V
SS
NC
V
SS
BW
A
V
SS
V
SS
V
SS
NC
A
NC
6
A
CE
3
A
DQP
B
DQ
B
DQ
B
DQ
B
DQ
B
V
DD
DQ
A
DQ
A
DQ
A
DQ
A
DQP
A
A
NC/36M
NC
7
V
DDQ
NC/576M
NC/1G
DQ
B
DQ
B
V
DDQ
DQ
B
DQ
B
V
DDQ
DQ
A
DQ
A
V
DDQ
DQ
A
DQ
A
NC
ZZ
V
DDQ
Figure 3. 165-Ball FBGA
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
NC/288M
NC/144M
DQP
C
DQ
C
DQ
C
DQ
C
DQ
C
NC
DQ
D
DQ
D
DQ
D
DQ
D
DQP
D
NC
MODE
2
A
A
NC
DQ
C
DQ
C
DQ
C
DQ
C
V
SS
DQ
D
DQ
D
DQ
D
DQ
D
NC
NC/72M
NC/36M
3
CE1
CE2
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
4
BW
C
BW
D
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
5
BW
B
BW
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
NC
NC
6
CE
3
CLK
7
BWE
GW
8
ADSC
OE
9
ADV
ADSP
10
A
A
NC/1G
DQ
B
DQ
B
DQ
B
DQ
B
NC
DQ
A
DQ
A
DQ
A
DQ
A
NC
A
A
11
NC
NC/576M
DQP
B
DQ
B
DQ
B
DQ
B
DQ
B
ZZ
DQ
A
DQ
A
DQ
A
DQ
A
DQP
A
NC/9M
A
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC/18M
A1
A0
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
NC
NC
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
A
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
NC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
A
A
A
A
Document #: 38-05516 Rev. *F
Page 4 of 22
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CY7C1347G
Table 1. Pin Definitions
Name
A
0
,A
1
,A
IO
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-Clock
Input-
Synchronous
Input-
Synchronous
Input-
Synchronous
Input-
Asynchronous
Input-
Synchronous
Input-
Synchronous
Description
Address Inputs Used to Select One of the 128K Address Locations.
Sampled at the rising edge
of the CLK if ADSP or ADSC is active LOW, and CE
1
, CE
2
, and CE
3
are sampled active. A
[1:0]
feeds
the 2-bit counter.
Byte Write Select Inputs, Active LOW.
Qualified with BWE to conduct byte writes to the SRAM.
Sampled on the rising edge of CLK.
Global Write Enable Input, Active LOW.
When asserted LOW on the rising edge of CLK, a global
write is conducted (ALL bytes are written, regardless of the values on BW
[A:D]
and BWE).
Byte Write Enable Input, Active LOW.
Sampled on the rising edge of CLK. This signal must be
asserted LOW to conduct a byte write.
Clock Input.
Used to capture all synchronous inputs to the device. Also used to increment the burst
counter when ADV is asserted LOW, during a burst operation.
Chip Enable 1 Input, Active LOW.
Sampled on the rising edge of CLK. Used in conjunction with CE
2
and CE
3
to select or deselect the device. ADSP is ignored if CE
1
is HIGH. CE
1
is sampled only when
a new external address is loaded.
Chip Enable 2 Input, Active HIGH.
Sampled on the rising edge of CLK. Used in conjunction with CE
1
and CE
3
to select or deselect the device. CE
2
is sampled only when a new external address is loaded.
Chip Enable 3 Input, Active LOW.
Sampled on the rising edge of CLK. Used in conjunction with CE
1
and CE
2
to select or deselect the device. CE
3
is sampled only when a new external address is loaded.
Output Enable, Asynchronous Input, Active LOW.
Controls the direction of the IO pins. When LOW,
the IO pins behave as outputs. When deasserted HIGH, IO pins are tri-stated, and act as input data
pins. OE is masked during the first clock of a read cycle when emerging from a deselected state.
Advance Input Signal, Sampled on the Rising Edge of CLK.
When asserted, it automatically
increments the address in a burst cycle.
Address Strobe from Processor, Sampled on the Rising Edge of CLK.
When asserted LOW,
addresses presented to the device are captured in the address registers. A
[1:0]
are also loaded into the
burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored
when CE
1
is deasserted HIGH.
Address Strobe from Controller, Sampled on the Rising Edge of CLK.
When asserted LOW,
addresses presented to the device are captured in the address registers. A
[1:0]
are also loaded into the
burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized.
ZZ “Sleep” Input.
This active HIGH input places the device in a non-time-critical “sleep” condition with
data integrity preserved. During normal operation, this pin must be LOW or left floating. ZZ pin has an
internal pull down.
Bidirectional Data IO Lines.
As inputs, they feed into an on-chip data register that is triggered by the
rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the
addresses presented during the previous clock rise of the read cycle. The direction of the pins is
controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPs
are placed in a tri-state condition.
Power Supply Inputs to the Core of the Device
Ground for the Core of the Device
Power Supply for the IO circuitry
Ground for the IO circuitry
Selects Burst Order.
When tied to GND selects linear burst sequence. When tied to V
DDQ
or left
floating selects interleaved burst sequence. This is a strap pin and must remain static during device
operation. Mode pin has an internal pull up.
No Connects.
Not internally connected to the die. NC/9M, NC/18M, NC/36M, NC/72M, NC/144M,
NC/288M, NC/576M, and NC/1G are address expansion pins that are not internally connected to the
die.
BW
A,
BW
B,
BW
C,
BW
D
GW
BWE
CLK
CE
1
CE
2
CE
3
OE
ADV
ADSP
ADSC
Input-
Synchronous
Input-
Asynchronous
IO-
Synchronous
ZZ
DQ
A,
DQ
B
DQ
C,
DQ
D
DQP
A,
DQP
B,
DQP
C,
DQP
D
V
DD
V
SS
V
DDQ
V
SSQ
MODE
Power Supply
Ground
IO Power Supply
IO Ground
Input-
Static
–
NC, NC/9M,
NC/18M,
NC/36M,
NC/72M,
NC/144M,
NC/288M,
NC/576M,
NC/1G
Document #: 38-05516 Rev. *F
Page 5 of 22
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