74ALVT162823
Rev. 3 — 23 January 2018
18-bit bus-interface D-type flip-flop with reset and enable with
30 Ω termination resistors; 3-state
Product data sheet
1
General description
The 74ALVT162823 18-bit bus interface register is designed to eliminate the extra
packages required to buffer existing registers and provide extra data width for wider data
or address paths of buses carrying parity.
The 74ALVT162823 has two 9-bit wide buffered registers with clock enable (nCE) and
master reset (nMR) which are ideal for parity bus interfacing in high microprogrammed
systems.
The registers are fully edge-triggered. The state of each D input, one set-up time before
the LOW-to-HIGH clock transition is transferred to the corresponding Q output of the
flip-flop.
The 74ALVT162823 is designed with 30 Ω series resistance in both the pull-up and
pull-down output structures. This design reduces line noise in applications such as
memory address drivers, clock drivers, and bus receivers or transmitters.
2
Features and benefits
•
Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops
•
5 V I/O compatible
•
Ideal where high speed, light loading or increased fan-in are required with MOS
microprocessors
•
Bus hold data inputs eliminate the need for external pull-up resistors to hold unused
inputs
•
Live insertion and extraction permitted
•
Power-up 3-state
•
Power-up reset
•
Output capability: +12 mA to −12 mA
•
Outputs include series resistance of 30 Ω making external termination resistors
unnecessary
•
Latch-up protection:
–
JESD78: exceeds 500 mA
•
ESD protection:
–
MIL STD 883, method 3015: exceeds 2000 V
–
MM: exceeds 200 V
Nexperia
18-bit bus-interface D-type flip-flop with reset and enable with 30 Ω termination resistors; 3-state
74ALVT162823
3
Ordering information
Package
Temperature range Name
Description
plastic thin shrink small outline package; 56 leads;
body width 6.1 mm
Version
SOT364-1
TSSOP56
Table 1. Ordering information
Type number
74ALVT162823DGG −40 °C to +85 °C
4
Functional diagram
1OE
1MR
1CE
1CP
2OE
2MR
2CE
2CP
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2
1
55
56
27
28
30
29
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
8D
5,6
EN1
R2
G3
3C4
EN5
R6
G7
7C8
4D
1,2
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
001aad242
V
CC
data input
to internal circuit
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
001aad244
27 Ω
27 Ω
output
VCC
VCC
001aad245
Figure 2. Bus hold circuit
Figure 1. IEC logic symbol
Figure 3. Schematic of each output
74ALVT162823
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 23 January 2018
2 / 18
Nexperia
nCE
nD0
nD1
nD2
nD3
nD4
nD5
nD6
nD7
nD8
74ALVT162823
18-bit bus-interface D-type flip-flop with reset and enable with 30 Ω termination resistors; 3-state
nCP
CP
nD
R
Q
CP
nD
R
Q
CP
nD
R
Q
CP
nD
R
Q
CP
nD
R
Q
CP
nD
R
Q
CP
nD
R
Q
CP
nD
R
Q
CP
nD
R
Q
nMR
nOE
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
nQ8
001aad243
Figure 4. Logic diagram
74ALVT162823
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 23 January 2018
3 / 18
Nexperia
18-bit bus-interface D-type flip-flop with reset and enable with 30 Ω termination resistors; 3-state
74ALVT162823
5
Pinning information
5.1 Pinning
1MR
1OE
1Q0
GND
1Q1
1Q2
V
CC
1Q3
1Q4
1
2
3
4
5
6
7
8
9
56 1CP
55 1CE
54 1D0
53 GND
52 1D1
51 1D2
50 V
CC
49 1D3
48 1D4
47 1D5
46 GND
45 1D6
44 1D7
43 1D8
42 2D0
41 2D1
40 2D2
39 GND
38 2D3
37 2D4
36 2D5
35 V
CC
34 2D6
33 2D7
32 GND
31 2D8
30 2CE
29 2CP
001aab433
1Q5 10
GND 11
1Q6 12
1Q7 13
1Q8 14
2Q0 15
2Q1 16
2Q2 17
GND 18
2Q3 19
2Q4 20
2Q5 21
V
CC
22
2Q6 23
2Q7 24
GND 25
2Q8 26
2OE 27
2MR 28
74ALVT162823
Figure 5. Pin configuration
74ALVT162823
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 23 January 2018
4 / 18
Nexperia
18-bit bus-interface D-type flip-flop with reset and enable with 30 Ω termination resistors; 3-state
74ALVT162823
5.2 Pin description
Table 2. Pin description
Symbol
1D0, 1D1, 1D2, 1D3, 1D4,
1D5, 1D6, 1D7, 1D8
1Q0, 1Q1, 1Q2, 1Q3, 1Q4,
1Q5, 1Q6, 1Q7, 1Q8
2D0, 2D1, 2D2, 2D3, 2D4,
2D5, 2D6, 2D7, 2D8
2Q0, 2Q1, 2Q2, 2Q3, 2Q4,
2Q5, 2Q6, 2Q7, 2Q8
1MR, 2MR
1OE, 2OE
1CP, 2CP
1CE, 2CE
GND
V
CC
Pin
54, 52, 51, 49, 48,
47, 45, 44, 43
3, 5, 6, 8, 9,
10, 12, 13, 14
42, 41, 40, 38, 37,
36, 34, 33, 31
15, 16, 17, 19, 20,
21, 23, 24, 26
1, 28
2, 27
56, 29
55, 30
4, 11, 18, 25,
32, 39, 46, 53
7, 22, 35, 50
Description
data inputs
data outputs
data inputs
data outputs
master reset input (active-LOW)
output enable inputs (active LOW)
clock pulse inputs (active rising edge)
clock enable input (active-LOW)
ground (0 V)
supply voltage
6
Functional description
[1]
Table 3. Function table
Operating mode
Clear
Load and read data
Hold
High-impedance
Input
nOE
L
L
L
H
nMR
L
H
H
X
nCE
X
L
H
X
nCP
X
↑
NC
X
nDn
X
h
l
X
X
Output
nQn
L
H
L
NC
Z
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition;
NC = no change;
X = don’t care;
Z = high-impedance OFF-state;
↑ = LOW-to-HIGH clock transition;
74ALVT162823
All information provided in this document is subject to legal disclaimers.
© Nexperia B.V. 2018. All rights reserved.
Product data sheet
Rev. 3 — 23 January 2018
5 / 18
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