(Pin 24 to Pin 12).................................................−0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
[1]
....................................... −0.5V
to V
CC
+ 0.5V
DC Input Voltage
[1]
.................................... −0.5V
to V
CC
+ 0.5V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current .................................................... >200 mA
Operating Range
Range
Commercial
Ambient
Temperature
0
°
C to +70
°
C
V
CC
5V
±
10%
Electrical Characteristics
Over the Operating Range
7C197-12
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
I
SB1
I
SB2
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[1]
Input Load Current
Output Leakage Current
Output Short
Circuit Current
[2]
V
CC
Operating
Supply Current
Automatic CE Power-Down
Current—TTL Inputs
[3]
Automatic CE Power-Down
Current—CMOS Inputs
[3]
GND < V
I
< V
CC
GND < V
O
< V
CC
, Output Disabled
V
CC
= Max., V
OUT
= GND
V
CC
= Max., I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Max. V
CC
, CE > V
IH
, V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Max. V
CC
, CE > V
CC
−
0.3V,
V
IN
> V
CC
−
0.3V or V
IN
< 0.3V
Test Conditions
V
CC
= Min., I
OH
=
−4.0
mA
V
CC
= Min.
I
OL
=12.0 mA
2.2
−0.5
−5
−5
Min.
2.4
0.4
V
CC
+ 0.3V
0.8
+5
+5
−300
150
30
10
2.2
−0.5
−5
−5
Max.
7C197-15
Min.
2.4
0.4
V
CC
+0.3V
0.8
+5
+5
−300
140
30
10
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
mA
Notes:
1. V
(min.)
=
−
2.0V for pulse durations of less than 20 ns.
2. Not more than one output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
3. A pull-up resistor to V
CC
on the CE input is required to keep the device deselected during V
CC
power-up, otherwise I
SB
will exceed values given.
2
CY7C197
Electrical Characteristics
Over the Operating Range (continued)
7C197-20
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
I
SB1
I
SB2
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
[1]
Input Load Current
Output Leakage Current
Output Short
Circuit Current
[2]
V
CC
Operating
Supply Current
Automatic CE Power Down
Current—TTL Inputs
[3]
Automatic CE Power-Down
Current—CMOS Inputs
[3]
GND < V
I
< V
CC
GND < V
O
< V
CC
, Output Disabled
V
CC
= Max., V
OUT
= GND
V
CC
= Max., I
OUT
= 0 mA,
f = f
MAX
= 1/t
RC
Max. V
CC
, CE > V
IH
, V
IN
> V
IH
or
V
IN
< V
IL
, f = f
MAX
Max. V
CC
, CE > V
CC
−
0.3V,
V
IN
> V
CC
−
0.3V or V
IN
< 0.3V
Test Conditions
V
CC
= Min., I
OH
=
−4.0
mA
V
CC
= Min.
I
OL
=12.0mA
2.2
−0.5
−5
−5
Min.
2.4
0.4
V
CC
+ 0.3V
0.8
+5
+5
−300
135
30
15
2.2
−0.5
−5
−5
Max.
7C197-25, 35, 45
Min.
2.4
0.4
V
CC
+ 0.3V
0.8
+5
+5
−300
95
30
15
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
mA
Capacitance
[4]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25
°
C, f = 1 MHz,
V
CC
= 5.0V
Max.
8
10
Unit
pF
pF
AC Test Loads and Waveforms
[5]
R1 329Ω
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
Equivalent to:
5V
OUTPUT
R2
5 pF
202Ω
(255Ω MIL) INCLUDING
JIG AND
SCOPE
R2
255Ω
(255Ω MIL)
3.0V
10%
GND
< t
r
< t
r
C197-5
R1 329Ω
ALL INPUT PULSES
90%
90%
10%
(a)
(b)
C197-4
THÉVENIN EQUIVALENT
125Ω
OUTPUT
1.90V
Commercial
Notes:
4. Tested initially and after any design or process changes that may affect these parameters.
5. t
r
= < 3 ns for the -12 and -15 speeds. t
r
= < 5 ns for the -20 and slower speeds.
3
CY7C197
Switching Characteristics
Over the Operating Range
[6]
7C197-12
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
LZCE
t
HZCE
t
PU
t
PD
Read Cycle Time
Address to
Data Valid
Output Hold from
Address Change
CE LOW to
Data Valid
CE LOW to
Low Z
[7]
CE HIGH to
High Z
[7, 8]
CE LOW to
Power-Up
CE HIGH to
Power-Down
Write Cycle Time
CE LOW to
Write End
Address Set-Up to
Write End
Address Hold from
Write End
Address Set-Up to
Write Start
WE Pulse Width
Data Set-Up to
Write End
Data Hold from
Write End
WE HIGH to
Low Z
[7]
WE LOW to
High Z
[7,8]
12
9
9
0
0
8
8
0
2
7
0
12
3
5
0
15
3
12
3
7
12
12
3
15
3
0
0
20
9
15
15
3
20
3
0
0
20
11
20
20
3
25
3
0
0
25
15
25
25
3
35
3
0
0
30
15
35
35
3
45
45
45
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
7C197-15
Min.
Max.
7C197-20
Min.
Max.
7C197-25
Min.
Max.
7C197-35
Min.
Max.
7C197-45
Min.
Max.
Unit
WRITE CYCLE
[9]
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
15
10
10
0
0
9
9
0
2
7
20
15
15
0
0
15
10
0
3
0
10
25
20
20
0
0
20
15
0
3
0
11
35
30
30
0
0
25
17
0
3
0
15
45
40
40
0
0
30
20
0
3
0
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
6. Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 and slower speeds, timing reference levels of
1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified I
OL
/I
OH
and 30-pF load capacitance.
7. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
and t
HZWE
is less than t
LZWE
for any given device.
8. t
HZCE
and t
HZWE
are specified with C
L
= 5 pF as in part (b) in AC Test Loads and Waveforms. Transition is measured
±500
mV from steady-state voltage.
9. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
R. E. Crochiere and L. R. Rabiner
Multirate Digital Signal Processing
Prentice-Hall, 1983, ISBN 0-13-605162-6.
This book is the only real reference for filter banks and mul ......
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