2GB, 4GB (x64, DR): 240-Pin DDR3 SDRAM UDIMM
Features
DDR3 SDRAM UDIMM
MT16JTF25664AZ – 2GB
MT16JTF51264AZ – 4GB
For component data sheets, refer to Micron’s Web site:
www.micron.com
Features
• DDR3 functionality and operations supported as per
component data sheet
• 240-pin, unbuffered dual in-line memory module
(UDIMM)
• Fast data transfer rates: PC3-12800, PC3-10600,
PC3-8500, or PC3-6400
• 2GB (256 Meg x 64), 4GB (512 Meg x 64)
• Vdd = Vddq = +1.5V ± 0.75V
• Vddspd = +3.0V to +3.6V
• Reset pin for improved system stability
• Nominal and dynamic on-die termination (ODT) for
data, strobe, and mask signals
• Dual rank
• 8 internal device banks for concurrent operation
• Fixed burst length of 8 (BL8) and burst chop of
4 (BC4) via the mode register
• Adjustable data-output drive strength
• Serial presence-detect (SPD) EEPROM
• Gold edge contacts
• Halogen-free
• Addresses are mirrored for second rank
• Fly-by topology
• Terminated control, command, and address bus
Figure 1:
240-Pin UDIMM (MO-269 R/C B)
Module Height: 30.0 mm (1.18 in)
Options
• Operating temperature
1
–
Commercial (0°C
≤
T
A
≤
+70°C)
–
Industrial (–40°C
≤
T
A
≤
+85°C)
• Package
–
240-pin DIMM (halogen-free)
• Frequency/CAS latency
–
1.25ns @ CL = 11 (DDR3-1600)
–
1.5ns @ CL = 9 (DDR3-1333)
–
1.87ns @ CL = 7 (DDR3-1066)
–
1.87ns @ CL = 8 (DDR3-1066)
2
–
2.5ns @ CL = 5 (DDR3-800)
2
–
2.5ns @ CL = 6 (DDR3-800)
2
Marking
None
I
Z
-1G6
-1G4
-1G1
-1G0
-80C
-80B
Notes: 1. Contact Micron for industrial temperature
module offerings.
2. Not recommended for new designs.
Table 1:
Key Timing Parameters
t
RCD
t
RP
t
RC
Data Rate (MT/s)
Speed
Industry
Grade Nomenclature CL = 11 CL = 10 CL = 9 CL = 8 CL = 7
-1G6
-1G4
-1G1
-1G0
-80C
-80B
PC3-12800
PC3-10600
PC3-8500
PC3-8500
PC3-6400
PC3-6400
1600
1333
1333
–
–
–
–
1333
1333
–
–
–
–
1066
1066
–
1066
–
–
1066
800
1066
800
–
–
CL = 6
800
800
800
800
800
800
CL = 5
667
667
667
667
800
667
(ns)
13.125
13.125
13.125
15
12.5
15
(ns)
13.125
13.125
13.125
15
12.5
15
(ns)
48.75
49.5
50.625
52.5
50
52.5
PDF: 09005aef837cdd2d/Source: 09005aef837cdc74
JTF16C_256_512x64AZ.fm - Rev. A 2/09 EN
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
2GB, 4GB (x64, DR): 240-Pin DDR3 SDRAM UDIMM
Features
Table 2:
Parameter
Refresh count
Row address
Device bank address
Device page size per bank
Device configuration
Column address
Module rank address
Addressing
2GB
8K
16K A[13:0]
8 BA[2:0]
1KB
1Gb (128 Meg x 8)
1K A[9:0]
2 S#[1:0]
4GB
8K
32K A[14:0]
8 BA[2:0]
1KB
2Gb (256 Meg x 8)
1K A[9:0]
2 S#[1:0]
Table 3:
Part Numbers and Timing Parameters 2GB Modules
Base device: MT41J128M8,
1
1Gb DDR3 SDRAM
Module
Density
2GB
2GB
2GB
2GB
2GB
2GB
Module
Bandwidth
12.8 GB/s
10.6 GB/s
8.5 GB/s
8.5 GB/s
6.4 GB/s
6.4 GB/s
Memory Clock/
Data Rate
1.25ns/1600 MT/s
1.5ns/1333 MT/s
1.87ns/1066 MT/s
1.87ns/1066 MT/s
2.5ns/800 MT/s
2.5ns/800 MT/s
CL-
t
RCD-
t
RP
(Clock Cycles)
11-11-11
9-9-9
7-7-7
8-8-8
5-5-5
6-6-6
Part Number
2
Configuration
256 Meg x 64
256 Meg x 64
256 Meg x 64
256 Meg x 64
256 Meg x 64
256 Meg x 64
MT16JTF25664A(I)Z-1G6__
MT16JTF25664A(I)Z-1G4__
MT16JTF25664A(I)Z-1G1__
MT16JTF25664A(I)Z-1G0__
MT16JTF25664A(I)Z-80C__
MT16JTF25664A(I)Z-80B__
Table 4:
Part Numbers and Timing Parameters 4GB Modules
Base device: MT41J256M8,
1
2Gb DDR3 SDRAM
Module
Density
4GB
4GB
4GB
4GB
4GB
4GB
Module
Bandwidth
12.8 GB/s
10.6 GB/s
8.5 GB/s
8.5 GB/s
6.4 GB/s
6.4 GB/s
Memory Clock/
Data Rate
1.25ns/1600 MT/s
1.5ns/1333 MT/s
1.87ns/1066 MT/s
1.87ns/1066 MT/s
2.5ns/800 MT/s
2.5ns/800 MT/s
CL-
t
RCD-
t
RP
(Clock Cycles)
11-11-11
9-9-9
7-7-7
8-8-8
5-5-5
6-6-6
Part
Number
2
Configuration
512 Meg x 64
512 Meg x 64
512 Meg x 64
512 Meg x 64
512 Meg x 64
512 Meg x 64
MT16JTF51264A(I)Z-1G6__
MT16JTF51264A(I)Z-1G4__
MT16JTF51264A(I)Z-1G1__
MT16JTF51264A(I)Z-1G0__
MT16JTF51264A(I)Z-80C__
MT16JTF51264A(I)Z-80B__
Notes:
1. Data sheets for the base device parts can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown), designating component and PCB
revisions. Consult factory for current revision codes. Example: MT16JTF51264AY-1G1B1.
PDF: 09005aef837cdd2d/Source: 09005aef837cdc74
JTF16C_256_512x64AZ.fm - Rev. A 2/09 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
2GB, 4GB (x64, DR): 240-Pin DDR3 SDRAM UDIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Table 5:
Pin Assignments
240-Pin UDIMM Front
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Vrefdq
Vss
DQ0
DQ1
Vss
DQS0#
DQS0
Vss
DQ2
DQ3
Vss
DQ8
DQ9
Vss
DQS1#
DQS1
Vss
DQ10
DQ11
Vss
DQ16
DQ17
Vss
DQS2#
DQS2
Vss
DQ18
DQ19
Vss
DQ24
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
DQ25
Vss
DQS3#
DQS3
Vss
DQ26
DQ27
Vss
NC
NC
Vss
NC
NC
Vss
NC
NC
Vss
NC
NC
CKE0
Vdd
BA2
NC
Vdd
A11
A7
Vdd
A5
A4
Vdd
Notes:
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
A2
Vdd
CK1
CK1#
Vdd
Vdd
Vrefca
NC
Vdd
A10
BA0
Vdd
WE#
CAS#
Vdd
S1#
ODT1
Vdd
NC
Vss
DQ32
DQ33
Vss
DQS4#
DQS4
Vss
DQ34
DQ35
Vss
DQ40
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
DQ41
Vss
DQS5#
DQS5
Vss
DQ42
DQ43
Vss
DQ48
DQ49
Vss
DQS6#
DQS6
Vss
DQ50
DQ51
Vss
DQ56
DQ57
Vss
DQS7#
DQS7
Vss
DQ58
DQ59
Vss
SA0
SCL
SA2
Vtt
240-Pin UDIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
Vss
DQ4
DQ5
Vss
DM0
NC
Vss
DQ6
DQ7
Vss
DQ12
DQ13
Vss
DM1
NC
Vss
DQ14
DQ15
Vss
DQ20
DQ21
Vss
DM2
NC
Vss
DQ22
DQ23
Vss
DQ28
DQ29
151
Vss
152
DM3
153
NC
154
Vss
155
DQ30
156
DQ31
157
Vss
158
NC
159
NC
160
Vss
161
NC
162
NC
163
Vss
164
NC
165
NC
166
Vss
167
NC
168 RESET#
169
CKE1
170
Vdd
171
NC
172 NC/A14
1
173
Vdd
174
A12
175
A9
176
Vdd
177
A8
178
A6
179
Vdd
180
A3
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
A1
Vdd
Vdd
CK0
CK0#
Vdd
NC
A0
Vdd
BA1
Vdd
RAS#
S0#
Vdd
ODT0
A13
Vdd
NC
Vss
DQ36
DQ37
Vss
DM4
NC
Vss
DQ38
DQ39
Vss
DQ44
DQ45
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Vss
DM5
NC
Vss
DQ46
DQ47
Vss
DQ52
DQ53
Vss
DM6
NC
Vss
DQ54
DQ55
Vss
DQ60
DQ61
Vss
DM7
NC
Vss
DQ62
DQ63
Vss
Vddspd
SA1
SDA
Vss
Vtt
1. Pin 172 is NC for 2GB and A14 for 4GB.
PDF: 09005aef837cdd2d/Source: 09005aef837cdc74
JTF16C_256_512x64AZ.fm - Rev. A 2/09 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
2GB, 4GB (x64, DR): 240-Pin DDR3 SDRAM UDIMM
Pin Assignments and Descriptions
Table 6:
Symbol
A[14:0]
Pin Description
Type
Input
Description
BA[2:0]
CK[1:0]
CK#[1:0]
CKE[1:0]
DM[7:0]
ODT[1:0]
RAS#, CAS#,
WE#
RESET#
S#[1:0]
SA[2:0]
SCL
DQ[63:0]
DQS[7:0]
DQS#[7:0]
SDA
Vdd
Vddspd
Vrefca
Vrefdq
Vss
Vtt
NC
Address inputs:
Provide the row address for ACTIVATE commands, and the column address
and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the
memory array in the respective bank. A10 is sampled during a PRECHARGE command to
determine whether the PRECHARGE applies to one bank (A10 LOW, bank selected by
BA[2:0]) or all banks (A10 HIGH). If only one bank is to be precharged, the bank is selected
by BA. A12 is also used for BC4/BL8 identification as “BL on-the-fly” during CAS commands.
The address inputs also provide the op-code during the mode register command set
.
A[13:0]
(2GB); A[14:0] (4GB).
Input
Bank address inputs:
BA[2:0] define the device bank to which an ACTIVATE, READ, WRITE,
or PRECHARGE command is being applied. BA[2:0] define which mode register (MR0, MR1,
MR2, and MR3) is loaded during the LOAD MODE command.
Input
Clock:
CK and CK# are differential clock inputs. All control, command, and address input
signals are sampled on the crossing of the positive edge of CK and the negative edge of
CK#.
Input
Clock enable:
CKE enables (registered HIGH) and disables (registered LOW) internal
circuitry and clocks on the DRAM.
Input
Input data mask:
DM is an input mask signal for write data. Input data is masked when
DM is sampled HIGH, along with the input data, during a write access. DM is sampled on
both edges of DQS. Although the DM pins are input-only, the DM loading is designed to
match that of the DQ and DQS pins.
Input
On-die termination:
ODT enables (registered HIGH) and disables (registered LOW)
termination resistance internal to the DRAM. When enabled in normal operation, ODT is
only applied to the following pins: DQ, DQS, DQS#, and DM. The ODT input will be ignored
if disabled via the LOAD MODE command.
Input
Command inputs:
RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Input
Reset:
RESET# is an active LOW CMOS input referenced to Vss. The RESET# input receiver is
(LVCMOS) a CMOS input defined as a rail-to-rail signal with DC HIGH
≥
0.8 x Vdd and DC LOW
≤
0.2 x
Vdd.
Input
Chip select:
S# enables (registered LOW) and disables (registered HIGH) the command
decoder.
Input
Serial address inputs:
These pins are used to configure the SPD EEPROM address range.
Input
Serial clock for SPD EEPROM:
SCL is used to synchronize communication to and from the
SPD EEPROM.
I/O
Data input/output:
Bidirectional data bus.
I/O
Data strobe:
DQS and DQS# are differential data strobes. Output with read data. Edge-
aligned with read data. Input with write data. Center-aligned with write data.
I/O
Serial data:
SDA is a bidirectional pin used to transfer addresses and data into and out of
the SPD EEPROM on the module on the I2C bus.
Supply
Power supply:
1.5V ±0.075V. The component Vdd and Vddq are connected to the module
Vdd.
Supply
SPD EEPROM positive power supply:
+3.0V to +3.6V.
Supply
Reference voltage:
Control, command, and address. Vdd/2.
Supply
Reference voltage:
DQ, DM. Vdd/2.
Supply
Ground.
Supply
Termination voltage:
Used for control, command, and address. Vdd/2.
–
No connect:
These pins are not connected on the module.
PDF: 09005aef837cdd2d/Source: 09005aef837cdc74
JTF16C_256_512x64AZ.fm - Rev. A 2/09 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
2GB, 4GB (x64, DR): 240-Pin DDR3 SDRAM UDIMM
DQ Map
DQ Map
DQ lines from component to module are shown in Table 6.
Table 7:
Component
Reference
Number
U1
Component-to-Module-DQ Map
Component
DQ
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Module
DQ
2
5
7
1
6
4
3
0
18
21
23
17
22
20
19
16
34
37
39
33
38
36
35
32
50
53
55
49
54
52
51
48
61
58
57
63
56
59
60
62
45
42
41
47
40
43
44
46
Module Pin
Number
9
123
129
4
128
122
10
3
27
141
147
22
146
140
28
21
87
201
207
82
206
200
88
81
105
219
225
100
224
218
106
99
228
114
109
234
108
115
227
233
210
96
91
216
90
97
209
215
Component
Reference
Number
U2
Component
DQ
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Module
DQ
10
13
15
9
14
12
11
8
26
29
31
25
30
28
27
24
42
45
47
41
46
44
43
40
58
61
63
57
62
60
59
56
53
50
49
55
48
51
52
54
37
34
33
39
32
35
36
38
Module Pin
Number
18
132
138
13
137
131
19
12
36
150
156
31
155
149
37
30
96
210
216
91
215
209
97
90
114
228
234
109
233
227
115
108
219
105
100
225
99
106
218
224
201
87
82
207
81
88
200
206
U3
U4
U5
U6
U7
U8
U10
U11
U12
U13
PDF: 09005aef837cdd2d/Source: 09005aef837cdc74
JTF16C_256_512x64AZ.fm - Rev. A 2/09 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2008 Micron Technology, Inc. All rights reserved.
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