Integrated
Circuit
Systems, Inc.
ICS9DB104
(Not recommended for new designs)
Four Output Differential Buffer for PCI-Express
Recommended Application:
DB400 Intel Yellow Cover part with PCI-Express support.
Output Features:
•
4 - 0.7V current-mode differential output pairs
•
Supports zero delay buffer mode and fanout mode
•
Bandwidth programming available
Key Specifications:
•
Outputs cycle-cycle jitter: < 50ps
•
Outputs skew: < 50ps
•
+/- 300ppm frequency accuracy on output clocks
Features/Benefits:
•
Supports tight ppm accuracy clocks for Serial-ATA
•
Spread spectrum modulation tolerant, 0 to -0.5% down
spread and +/- 0.25% center spread
•
Supports undriven differential output pair in PD# and
SRC_STOP# for power management.
Pin Configuration
d
e
d s
n n
e g
m si
m de
o
c w
e e
r
t n
o
N
VDD
SRC_IN
SRC_IN#
GND
VDD
DIF_1
DIF_1#
OE_1
DIF_2
DIF_2#
VDD
BYPASS#/PLL
SCLK
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
r
o
f
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDDA
GNDA
IREF
GND
VDD
DIF_6
DIF_6#
OE_6
DIF_5
DIF_5#
VDD
HIGH_BW#
SRC_STOP#
PD#
28-pin SSOP & TSSOP
0767E—12/14/07
ICS9DB104
Integrated
Circuit
Systems, Inc.
ICS9DB104
(Not recommended for new designs)
Pin Description
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
PIN NAME
VDD
SRC_IN
SRC_IN#
GND
VDD
DIF_1
DIF_1#
OE_1
DIF_2
DIF_2#
VDD
BYPASS#/PLL
SCLK
SDATA
PD#
SRC_STOP#
HIGH_BW#
VDD
DIF_5#
DIF_5
OE_6
DIF_6#
DIF_6
VDD
GND
IREF
GNDA
VDDA
PIN TYPE
PWR
IN
IN
PWR
PWR
OUT
OUT
IN
OUT
OUT
PWR
IN
IN
I/O
IN
IN
IN
PWR
OUT
OUT
IN
OUT
OUT
PWR
PWR
OUT
PWR
PWR
DESCRIPTION
Power supply, nominal 3.3V
0.7 V Differential SRC TRUE input
0.7 V Differential SRC COMPLEMENTARY input
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock outputs
0.7V differential complement clock outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock outputs
0.7V differential complement clock outputs
Power supply, nominal 3.3V
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Asynchronous active low input pin used to power down the device. The
internal clocks are disabled and the VCO and the crystal are stopped.
Active low input to stop diff outputs.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
Power supply, nominal 3.3V
0.7V differential complement clock outputs
0.7V differential true clock outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
0.7V differential complement clock outputs
0.7V differential true clock outputs
Power supply, nominal 3.3V
Ground pin.
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
0767E—12/14/07
2
Integrated
Circuit
Systems, Inc.
ICS9DB104
(Not recommended for new designs)
General Description
ICS9DB104
follows the Intel DB400 Differential Buffer Specification. This buffer provides four SRC clocks for PCI-Express,
next generation I/O devices.
ICS9DB104
is driven by a differential input pair from a CK409/CK410 main clock generator, such
as the ICS952601 or ICS954101.
ICS9DB104
can run at speeds up to 200MHz. It provides ouputs meeting tight cycle-to-cycle
jitter (50ps) and output-to-output skew (50ps) requirements.
Block Diagram
2
OE1, OE6
SRC_IN
SRC_IN#
SPREAD
COMPATIBLE
PLL
STOP
LOGIC
4
DIF(1,2,5,6)
HIGH_BW#
SRC_STOP#
PD#
BYPASS#/PLL
SDATA
SCLK
CONTROL
LOGIC
IREF
Power Groups
Pin Number
VDD
GND
1
4
5,11,18,24
4,25
28
27
28
27
Description
SRC_IN/SRC_IN#
DIF Outputs
IREF
Analog VDD & GND for PLL core
0767E—12/14/07
3
Integrated
Circuit
Systems, Inc.
ICS9DB104
(Not recommended for new designs)
Absolute Max
Symbol
VDD_A
VDD_In
V
IL
V
IH
Ts
Tambient
Tcase
ESD prot
Parameter
3.3V Core Supply Voltage
3.3V Logic Supply Voltage
Input Low Voltage
Input High Voltage
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
human body model
Min
Max
4.6
4.6
V
DD
+0.5V
150
70
115
Units
V
V
V
V
°
C
°C
°C
V
GND-0.5
-65
0
2000
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70°C; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
V
IH
V
IL
I
IH
I
IL1
Input Low Current
I
IL2
Operating Supply Current
Powerdown Current
Input Frequency
3
Pin Inductance
1
Input Capacitance
1
CONDITIONS
MIN
TYP
3.3 V +/-5%
2
GND - 0.3
3.3 V +/-5%
V
IN
= V
DD
-5
V
IN
= 0 V; Inputs with no pull-up
-5
resistors
V
IN
= 0 V; Inputs with pull-up
-200
resistors
Full Active, C
L
= Full load;
all diff pairs driven
all differential pairs tri-stated
V
DD
= 3.3 V
80
100/133
166/200
MAX
UNITS NOTES
V
DD
+ 0.3
V
0.8
V
5
uA
uA
uA
200
40
12
220
7
5
6
mA
mA
mA
MHz
nH
pF
pF
MHz
MHz
1
33
10
300
5
5
ms
kHz
ns
us
ns
ns
3
1
1
1
1
1
1,2
1
1,3
1,3
1
2
I
DD3.3OP
I
DD3.3PD
F
i
L
pin
C
IN
C
OUT
Logic Inputs
1.5
Output pin capacitance
PLL Bandwidth when
PLL_BW=0
PLL Bandwidth
BW
PLL Bandwidth when
PLL_BW=1
From V
DD
Power-Up and after
1,2
T
STAB
input clock stabilization or de-
Clk Stabilization
assertion of PD# to 1st clock
Triangular Modulation
30
Modulation Frequency
DIF output enable after
Tdrive_SRC_STOP#
SRC_Stop# de-assertion
DIF output enable after
Tdrive_PD#
PD# de-assertion
Fall time of PD# and
Tfall
SRC_STOP#
Rise time of PD# and
Trise
SRC_STOP#
1
Guaranteed by design and characterization, not 100% tested in production.
2
See timing diagrams for timing requirements.
3
Time from deassertion until outputs are >200 mV
0767E—12/14/07
4
2
4
Integrated
Circuit
Systems, Inc.
ICS9DB104
(Not recommended for new designs)
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
T
A
= 0 - 70°C; V
DD
= 3.3 V +/-5%; C
L
=2pF, R
S
=33.2Ω, R
P
=49.9Ω,
Ι
REF
= 475Ω
PARAMETER
Current Source Output
Impedance
Voltage High
Voltage Low
Max Voltage
Min Voltage
Crossing Voltage (abs)
Crossing Voltage (var)
Long Accuracy
SYMBOL
Zo
1
CONDITIONS
V
O
= V
x
Statistical measurement on single
ended signal using oscilloscope
math function.
Measurement on single ended
signal using absolute value.
Variation of crossing over all
edges
see Tperiod min-max values
200MHz nominal
200MHz spread
166.66MHz nominal
166.66MHz spread
133.33MHz nominal
133.33MHz spread
100.00MHz nominal
100.00MHz spread
200MHz nominal
166.66MHz nominal/spread
133.33MHz nominal/spread
100.00MHz nominal/spread
V
OL
= 0.175V, V
OH
= 0.525V
V
OH
= 0.525V V
OL
= 0.175V
MIN
3000
660
-150
-300
250
TYP
MAX
UNITS
Ω
NOTES
1
1,3
VHigh
VLow
Vovs
Vuds
Vcross(abs)
d-Vcross
ppm
850
mV
150
1150
550
140
mV
mV
mV
ppm
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ps
ps
ps
ps
1,3
1
1
1
1
1,2
2
2
2
2
2
2
2
2
1,2
1,2
1,2
1,2
1
1
1
1
1
1
1
1
Average period
Tperiod
Absolute min period
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
Duty Cycle
T
absmin
t
r
t
f
d-t
r
d-t
f
d
t3
4.9985
4.9985
5.9982
5.9982
7.4978
7.4978
9.9970
9.9970
4.8735
5.8732
7.3728
9.8720
175
175
0
5.0015
5.0266
6.0018
6.0320
7.5023
5.4000
10.0030
10.0533
700
700
125
125
Measurement from differential
45
55
%
wavefrom
V
T
= 50%
t
sk3
50
ps
Skew
PLL mode,
50
ps
Measurement from differential
t
jcyc-cyc
Jitter, Cycle to cycle
wavefrom
BYPASS mode as additive jitter
50
ps
1
Guaranteed by design and characterization, not 100% tested in production.
2
All Long Term Accuracy and Clock Period specifications are guaranteed with the assumption that the input clock
complies with CK409/CK410 accuracy requirements
3
I
REF
= V
DD
/(3xR
R
). For R
R
= 475Ω (1%), I
REF
= 2.32mA. I
OH
= 6 x I
REF
and V
OH
= 0.7V @ Z
O
=50Ω.
0767E—12/14/07
5
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