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100331 Low Power Triple D-Type Flip-Flop
February 1990
Revised August 2000
100331
Low Power Triple D-Type Flip-Flop
General Description
The 100331 contains three D-type, edge-triggered master/
slave flip-flops with true and complement outputs, a Com-
mon Clock (CP
C
), and Master Set (MS) and Master Reset
(MR) inputs. Each flip-flop has individual Clock (CP
n
),
Direct Set (SD
n
) and Direct Clear (CD
n
) inputs. Data enters
a master when both CP
n
and CP
C
are LOW and transfers
to a slave when CP
n
or CP
C
(or both) go HIGH. The Master
Set, Master Reset and individual CD
n
and SD
n
inputs over-
ride the Clock inputs. All inputs have 50 k
Ω
pull-down
resistors.
Features
s
35% power reduction of the 100131
s
2000V ESD protection
s
Pin/function compatible with 100131
s
Voltage compensated operating range
= −
4.2V to
−
5.7V
s
Available to industrial grade temperature range
Ordering Code:
Order Number
100331SC
100331PC
100331QC
100331QI
Package Number
M24B
N24E
V28A
V28A
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
28-Lead Plastic Lead Chip Carrier (PLCC), JEDEC MO-047, 0.450 Square
Industrial Temperature Range (
−
40
°
C to
+
85
°
C)
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Symbol
Connection Diagrams
24-Pin DIP/SOIC
Pin Descriptions
Pin Names
CP
0
–CP
2
CP
C
D
0
–D
2
CD
0
–CD
2
SD
n
MR
MS
Q
0
-Q
2
Q
0
–Q
2
Description
Individual Clock Inputs
Common Clock Input
Data Inputs
Individual Direct Clear Inputs
Individual Direct Set Inputs
Master Reset Input
Master Set Input
Data Outputs
Complementary Data Outputs
28-Pin PLCC
© 2000 Fairchild Semiconductor Corporation
DS010262
www.fairchildsemi.com
100331
Truth Tables
Synchronous Operation
(Each Flip-Flop)
Inputs
D
n
L
H
L
H
X
X
X
CP
n
Outputs
MS
SD
n
L
L
L
L
L
L
L
MR
CD
n
L
L
L
L
L
L
L
Q
n
(t
+
1)
L
H
L
H
Q
n
(t)
Q
n
(t)
Q
n
(t)
D
n
X
X
X
CP
n
X
X
X
Asynchronous Operation
(Each Flip-Flop)
Inputs
CP
C
X
X
X
MS
SD
n
H
L
H
MR
CD
n
L
H
H
Outputs
Q
n
(t
+
1)
H
L
U
L
L
L
H
X
CP
C
L
L
L
X
H
H
=
HIGH Voltage Level
L
=
LOW Voltage Level
X
=
Don’t Care
U
=
Undefined
t
=
Time before CP Positive Transition
t
+
1
=
Time after CP Positive Transition
=
LOW-to-HIGH Transition
Logic Diagram
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2
100331
Absolute Maximum Ratings
(Note 1)
Storage Temperature (T
STG
)
Maximum Junction Temperature (T
J
)
Pin Potential to Ground Pin (V
EE
)
Input Voltage (DC)
Output Current
(DC Output HIGH)
ESD (Note 2)
−
65
°
C to
+
150
°
C
+
150
°
C
−
7.0V to
+
0.5V
V
EE
to
+
0.5V
Recommended Operating
Conditions
Case Temperature (T
C
)
Commercial
Industrial
Supply Voltage (V
EE
)
0
°
C to
+
85
°
C
−
40
°
C to
+
85
°
C
−
5.7V to
−
4.2V
−
50 mA
≤
2000V
Note 1:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum rating.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Note 2:
ESD testing conforms to MIL-STD-883, Method 3015.
Commercial Version
DC Electrical Characteristics
(Note 3)
V
EE
= −
4.2V to
−
5.7V, V
CC
=
V
CCA
=
GND, T
C
=
0°C to
+85°C
Symbol
Parameter
Min
Typ
V
OH
V
OL
V
OHC
V
OLC
V
IH
V
IL
I
IL
I
IH
I
EE
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input LOW Current
Input HIGH Current
Power Supply Current
−122
−1165
−1830
0.5
240
−65
−1025
−1830
−1035
−1610
−870
−1475
−955
−1705
Max
−870
−1620
Units
mV
mV
mV
mV
mV
mV
µA
µA
mA
V
IN
=
V
IH
(Max)
or V
IL
(Min)
V
IN
=
V
IH
(Min)
or V
IL
(Max)
Guaranteed HIGH Signal
for All Inputs
Guaranteed LOW Signal
for All Inputs
V
IN
=
V
IL
(Min)
V
IN
=
V
IH
(Max)
Inputs OPEN
Conditions
Loading with
50Ω to
−2.0V
Loading with
50Ω to
−2.0V
Note 3:
The specified limits represent the “worst case” value for the parameter. Since these values normally occur at the temperature extremes, additional
noise immunity and guardbanding can be achieved by decreasing the allowable system operating ranges. Conditions for testing shown in the tables are cho-
sen to guarantee operation under “worst case” conditions.
3
www.fairchildsemi.com
100331
Commercial Version
(Continued)
DIP AC Electrical Characteristics
V
EE
= −
4.2V to
−
5.7V, V
CC
=
V
CCA
=
GND
Symbol
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
TLH
t
THL
t
S
Transition Time
20% to 80%, 80% to 20%
Setup Time
D
n
CD
n
, SD
n
(Release Time)
MS, MR (Release Time)
t
H
t
PW
(H)
Hold Time D
n
Pulse Width HIGH
CP
n
, CP
C
, CD
n
,
SD
n
, MR, MS
2.00
2.00
2.00
ns
Figures 3, 4
0.40
1.30
2.30
0.5
0.40
1.30
2.30
0.5
0.40
1.30
2.30
0.7
ns
ns
Figure 4
Figure 5
Propagation Delay
MS, MR to Output
Parameter
Toggle Frequency
Propagation Delay
CP
C
to Output
Propagation Delay
CP
n
to Output
Propagation Delay
CD
n
, SD
n
to Output
T
C
=
0°C
Min
375
0.75
0.75
0.70
0.70
1.10
1.10
0.35
2.00
2.00
1.70
2.00
2.60
2.80
1.30
Max
T
C
= +25°C
Min
375
0.75
0.75
0.70
0.70
1.10
1.10
0.35
2.00
2.00
1.70
2.00
2.60
2.80
1.30
Max
T
C
= +85°C
Min
375
0.75
0.75
0.70
0.70
1.10
1.10
0.35
2.00
2.00
1.80
ns
2.00
2.60
ns
2.80
1.30
ns
CP
n
, CP
C
=
H
Figures 1, 3, 4
Figure 5
CP
n
, CP
C
=
H
Figures 1, 4
CP
n
, CP
C
=
L
Max
MHz
ns
Figures 1, 3
ns
CP
n
, CP
C
=
L
Figures 2, 3
Units
Conditions
SOIC and PLCC AC Electrical Characteristics
V
EE
= −
4.2V to
−
5.7V, V
CC
=
V
CCA
=
GND
Symbol
f
MAX
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
TLH
t
THL
t
S
Transition Time
20% to 80%, 80% to 20%
Setup Time
D
n
CD
n
, SD
n
(Release Time)
MS, MR (Release Time)
t
H
t
PW
(H)
Hold Time D
n
Pulse Width HIGH
CP
n
, CP
C
, CD
n
,
SD
n
, MR, MS
2.00
2.00
2.00
ns
Figures 3, 4
0.30
1.20
2.20
0.5
0.30
1.20
2.20
0.5
0.30
1.20
2.20
0.7
ns
ns
Propagation Delay
MS, MR to Output
Parameter
Toggle Frequency
Propagation Delay
CP
C
to Output
Propagation Delay
CP
n
to Output
Propagation Delay
CD
n
, SD
n
to Output
T
C
=
0°C
Min
400
0.75
0.75
0.70
0.80
1.10
1.10
0.35
1.80
1.80
1.50
1.80
2.40
2.60
1.10
Max
T
C
= +25°C
Min
400
0.75
0.75
0.70
0.70
1.10
1.10
0.35
1.80
1.80
1.50
1.80
2.40
2.60
1.10
Max
T
C
= +85°C
Min
400
0.75
0.75
0.70
0.70
1.10
1.10
0.35
1.80
1.80
1.60
ns
1.80
2.40
2.60
1.10
ns
CP
n
, CP
C
=
H
Figures 1, 4
ns
CP
n
, CP
C
=
L
CP
n
, CP
C
=
H
Figures 1, 3, 4
Figure 5
Figure 4
Figure 5
Max
MHz
ns
Figures 1, 3
ns
CP
n
, CP
C
=L
Figures 2, 3
Units
Conditions
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4
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