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TPS7A8101
SBVS179B – DECEMBER 2011 – REVISED AUGUST 2015
TPS7A8101 Low-Noise, Wide-Bandwidth, High PSRR,
Low-Dropout 1-A Linear Regulator
1 Features
•
•
•
1
3 Description
The TPS7A8101 low-dropout linear regulator (LDO)
offers very good performance in noise and power-
supply rejection ratio (PSRR) at the output. This LDO
uses an advanced BiCMOS process and a
PMOSFET pass device to achieve very low noise,
excellent transient response, and excellent PSRR
performance.
The TPS7A8101 device is stable with a 4.7-μF
ceramic output capacitor, and uses a precision
voltage reference and feedback loop to achieve a
worst-case accuracy of 3% over all load, line,
process, and temperature variations.
This device is fully specified over the temperature
range of T
J
= –40°C to 125°C and is offered in a 3-
mm × 3-mm, SON-8 package with a thermal pad.
Device Information
(1)
PART NUMBER
TPS7A8101
PACKAGE
SON (8)
BODY SIZE (NOM)
3.00 mm × 3.00 mm
•
•
•
•
•
•
•
Low-Dropout 1-A Regulator with Enable
Adjustable Output Voltage: 0.8 V to 6 V
Wide-Bandwidth High PSRR:
– 80 dB at 1 kHz
– 60 dB at 100 kHz
– 54 dB at 1 MHz
Low Noise: 23.5
μV
RMS
typical (100 Hz to
100 kHz)
Stable with a 4.7-μF Capacitance
Excellent Load and Line Transient Response
3% Overall Accuracy (Over Load, Line,
Temperature)
Overcurrent and Overtemperature Protection
Very Low Dropout: 170 mV Typical at 1 A
Package: 3-mm × 3-mm SON-8
2 Applications
•
•
•
Telecom Infrastructure
Audio
High-Speed I/F (PLL and VCO)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Circuit
V
IN
C
IN
EN
GND
IN
OUT
TPS7A8101
FB
NR
C
NR
V
EN
R
1
C
BYPASS
V
OUT
R
2
C
OUT
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS7A8101
SBVS179B – DECEMBER 2011 – REVISED AUGUST 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
Features
..................................................................
Applications
...........................................................
Description
.............................................................
Revision History.....................................................
Pin Configuration and Functions
.........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
1
1
1
2
3
4
4
4
4
4
5
6
8.1 Application Information............................................
13
8.2 Typical Application ..................................................
13
9 Power Supply Recommendations......................
15
10 Layout...................................................................
16
10.1
10.2
10.3
10.4
10.5
11.1
11.2
11.3
11.4
11.5
11.6
Layout Guidelines .................................................
Layout Example ....................................................
Thermal Protection................................................
Power Dissipation .................................................
Estimating Junction Temperature ........................
Device Support......................................................
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
16
16
16
17
17
19
19
19
19
19
19
11 Device and Documentation Support
.................
19
7
Detailed Description
............................................
11
7.1
7.2
7.3
7.4
11
11
11
12
8
Application and Implementation
........................
13
12 Mechanical, Packaging, and Orderable
Information
...........................................................
19
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (April 2012) to Revision B
•
Page
Added
ESD Ratings
table,
Feature Description
section,
Device Functional Modes, Application and Implementation
section,
Power Supply Recommendations
section,
Layout
section,
Device and Documentation Support
section, and
Mechanical, Packaging, and Orderable Information
section .................................................................................................
1
Changes from Original (December 2011) to Revision A
•
Page
Added new footnote 2 to Thermal Information table, changed footnote 3 .............................................................................
4
2
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TPS7A8101
Copyright © 2011–2015, Texas Instruments Incorporated
TPS7A8101
www.ti.com
SBVS179B – DECEMBER 2011 – REVISED AUGUST 2015
5 Pin Configuration and Functions
DRB PACKAGE
8-Pin SON With Exposed Thermal Pad
Top View
OUT
OUT
FB/SNS
GND
1
2
3
4
8
7
6
5
IN
IN
NR
EN
Pin Functions
PIN
NAME
EN
FB
GND
IN
NR
OUT
NO.
5
3
4, pad
7
8
6
1
2
I/O
DESCRIPTION
Driving this pin high turns on the regulator. Driving this pin low puts the regulator into shutdown mode.
Refer to the
Shutdown
section for more details. EN must not be left floating and can be connected to IN
if not used.
This pin is the input to the control-loop error amplifier and is used to set the output voltage of the device.
Ground
Unregulated input supply
Connect an external capacitor between this pin and ground to reduce output noise to very low levels.
The capacitor also slows down the V
OUT
ramp (RC softstart).
Regulator output. A 4.7-μF or larger capacitor of any type is required for stability.
I
I
—
I
—
O
Copyright © 2011–2015, Texas Instruments Incorporated
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3
TPS7A8101
SBVS179B – DECEMBER 2011 – REVISED AUGUST 2015
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted).
(1)
MIN
IN
Voltage
FB, NR
EN
OUT
Current
Temperature
(1)
(2)
OUT
Operating virtual junction, T
J
Storage, T
stg
–0.3
–0.3
–0.3
–0.3
–55
–55
MAX
7
3.6
V
IN
+ 0.3
(2)
7
A
°C
°C
150
150
V
UNIT
Internally Limited
Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-
maximum-rated conditions for extended periods my affect device reliability.
V
EN
absolute maximum rating is V
IN
+ 0.3 V or +7 V, whichever is smaller.
6.2 ESD Ratings
VALUE
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins
(1)
V
(ESD)
(1)
(2)
Electrostatic discharge
Charged device model (CDM), per JEDEC specification JESD22-C101, all
pins
(2)
±2000
±500
V
UNIT
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating free-air temperature range (unless otherwise noted)
MIN
V
I
I
O
T
A
Input voltage
Output current
Operating free air temperature
2.2
0
–40
MAX
6.5
1
125
UNIT
V
A
°C
6.4 Thermal Information
TPS7A8101
THERMAL METRIC
(1)
R
θJA
R
θJC(top)
R
θJB
ψ
JT
ψ
JB
R
θJC(bot)
(1)
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
DRV (SON)
8 PINS
47.8
53.9
23.4
1
23.5
7.4
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
UNIT
For more information about traditional and new thermal metrics, see the
Semiconductor and IC Package Thermal Metrics
application
report,
SPRA953.
4
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Copyright © 2011–2015, Texas Instruments Incorporated
TPS7A8101
www.ti.com
SBVS179B – DECEMBER 2011 – REVISED AUGUST 2015
6.5 Electrical Characteristics
Over the operating temperature range of T
J
= –40°C to +125°C, V
IN
= V
OUT(TYP)
+ 0.5 V or 2.2 V (whichever is greater), I
OUT
=
1 mA, V
EN
= 2.2 V, C
OUT
= 4.7
μF,
C
NR
= 0.01
μF,
and C
BYPASS
= 0
μF,
unless otherwise noted. TPS7A8101 is tested at V
OUT
= 0.8 V and V
OUT
= 6 V. Typical values are at T
J
= 25°C.
PARAMETER
V
IN
V
NR
Input voltage range
(1)
Internal reference
Output voltage range
V
OUT
V
OUT
+ 0.5 V
≤
V
IN
≤
6 V, V
IN
≥
2.5 V,
100 mA
≤
I
OUT
≤
500 mA, 0°C
≤
T
J
≤
85°C
V
OUT
+ 0.5 V
≤
V
IN
≤
6.5 V, V
IN
≥
2.2 V,
100 mA
≤
I
OUT
≤
1 A
V
OUT(NOM)
+ 0.5 V
≤
V
IN
≤
6.5 V, V
IN
≥
2.2 V,
I
OUT
= 100 mA
100 mA
≤
I
OUT
≤
1 A
V
OUT
+ 0.5 V
≤
V
IN
≤
6.5 V, V
IN
≥
2.2 V,
I
OUT
= 500 mA, V
FB
= GND or V
SNS
= GND
V
DO
Dropout voltage
(3)
V
OUT
+ 0.5 V
≤
V
IN
≤
6.5 V, V
IN
≥
2.5 V,
I
OUT
= 750 mA, V
FB
= GND or V
SNS
= GND
V
OUT
+ 0.5 V
≤
V
IN
≤
6.5 V, V
IN
≥
2.5 V,
I
OUT
= 1 A, V
FB
= GND or V
SNS
= GND
I
LIM
I
GND
I
SHDN
I
FB
Output current limit
Ground pin current
Shutdown current (I
GND
)
Feedback pin current
V
OUT
= 0.85 × V
OUT(NOM)
, V
IN
≥
3.3 V
I
OUT
= 1 mA
I
OUT
= 1 A
V
EN
≤
0.4 V, V
IN
≥
2.2 V, R
L
= 1 kΩ,
0°C
≤
T
J
≤
85°C
V
IN
= 6.5 V, V
FB
= 0.8 V
f = 100 Hz
f = 1 kHz
PSRR
Power-supply rejection ratio
V
IN
= 4.3 V, V
OUT
= 3.3 V,
I
OUT
= 750 mA
f = 10 kHz
f = 100 kHz
f = 1 MHz
V
n
Output noise voltage
BW = 100 Hz to 100 kHz,
V
IN
= 3.8 V, V
OUT
= 3.3 V,
I
OUT
= 100 mA, C
NR
= C
BYPASS
= 470 nF
2.2 V
≤
V
IN
≤
3.6 V, R
L
= 1 kΩ
3.6 V < V
IN
≤
6.5 V, R
L
= 1 kΩ
R
L
= 1 kΩ
V
IN
= V
EN
= 6.5 V
V
OUT(NOM)
= 3.3 V, V
OUT
= 0% to 90% V
OUT(NOM)
,
R
L
= 3.3 kΩ, C
OUT
= 10
μF,
C
NR
= 470 nF
V
IN
rising, R
L
= 1 kΩ
V
IN
falling, R
L
= 1 kΩ
Shutdown, temperature increasing
Reset, temperature decreasing
–40
1.86
1.2
1.35
0
0.02
80
2
75
160
140
125
2.10
0.4
1
0.2
0.02
80
82
78
60
54
23.5
μV
RMS
dB
1100
1400
60
TEST CONDITIONS
MIN
2.2
0.79
0.8
-2%
–3%
±0.3%
150
2
250
350
500
2000
100
350
2
1
mA
μA
μA
μA
mV
0.8
TYP
MAX
6.5
0.81
6
2%
3%
μV/V
μV/mA
UNIT
V
V
V
Output accuracy
(2)
ΔV
O(ΔVI)
ΔV
O(ΔIL)
Line regulation
Load regulation
V
EN(HI)
V
EN(LO)
I
EN(HI)
t
STR
UVLO
Enable high (enabled)
Enable low (shutdown)
Enable pin current, enabled
Start-up time
Undervoltage lockout
Hysteresis
Thermal shutdown temperature
Operating junction temperature
V
V
μA
ms
V
mV
°C
°C
°C
T
SD
T
J
(1)
(2)
(3)
Minimum V
IN
= V
OUT
+ V
DO
or 2.2 V, whichever is greater.
The TPS7A8101 does not include external resistor tolerances and it is not tested at this condition: V
OUT
= 0.8 V, 4.5V
≤
V
IN
≤
6.5 V, and
750 mA
≤
I
OUT
≤
1 A because the power dissipation is greater than the maximum rating of the package.
V
DO
is not measured for fixed output voltage devices with V
OUT
< 1.7 V because minimum V
IN
= 2.2 V.
Copyright © 2011–2015, Texas Instruments Incorporated
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Product Folder Links:
TPS7A8101
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