EQRA14E2H-18.33111M
REGULATORY COMPLIANCE
2011/65 +
2015/863
(Data Sheet downloaded on Sep 6, 2020)
191 SVHC
ITEM DESCRIPTION
Quartz Crystal Clock Oscillators XO (SPXO) LVCMOS (CMOS) 2.8Vdc 6 Pad 5.0mm x 7.0mm Ceramic Surface Mount (SMD)
18.33111MHz ±100ppm over -20°C to +70°C
ELECTRICAL SPECIFICATIONS
Nominal Frequency
Frequency Tolerance/Stability
Aging at 25°C
Supply Voltage
Input Current
Output Voltage Logic High (Voh)
Output Voltage Logic Low (Vol)
Rise/Fall Time
Duty Cycle
Load Drive Capability
Output Logic Type
Phase Noise
18.33111MHz
±100ppm Maximum over -20°C to +70°C (Inclusive of all conditions: Calibration Tolerance (at 25°C), Frequency
Stability over the Operating Temperature Range, Supply Voltage Change and Output Load Change)
±2ppm Maximum First Year, ±10ppm/10 Years Maximum
2.8Vdc ±5%
20mA Maximum (Unloaded)
90% of Vdd Minimum (IOH = -4mA)
10% of Vdd Maximum (IOL = +4mA)
3nSec Maximum (Measured at 10% to 90% of Waveform)
50 ±5(%) (Measured at 50% of Waveform)
15pF Maximum
CMOS
-64dBc/Hz at 10Hz offset; -96dBc/Hz at 100Hz offset; -124dBc/Hz at 1kHz offset; -131dBc/Hz at 10kHz offset; -
132dBc/Hz at 100kHz offset; -149dBc/Hz at 1MHz offset; -157dBc/Hz at 10MHz offset; -159dBc/Hz at 20MHz offset (All
Values are Typical)
Output Enable (OE)
90% of Vdd Minimum or No Connect to Enable Output
10% of Vdd Maximum to Disable Output (High Impedance)
100nSec Maximum
50nSec Maximum
15mA Maximum (Without Load (Pin 1 = Ground))
1.5pSec Maximum (Fj=12kHz to 20MHz (Random))
0.2pSec Typical
2pSec Typical
3pSec Maximum
30pSec Maximum
10mSec Maximum
-55°C to +125°C
Output Control Function
Output Control Input Voltage Logic
High (Vih)
Output Control Input Voltage Logic
Low (Vil)
Output Enable Time
Output Disable Time
Output Enable Current
RMS Phase Jitter
Period Jitter (Deterministic)
Period Jitter (Random)
Period Jitter (RMS)
Period Jitter (pk-pk)
Start Up Time
Storage Temperature Range
ENVIRONMENTAL & MECHANICAL SPECIFICATIONS
ESD Susceptibility
Fine Leak Test
Flammability
Gross Leak Test
Mechanical Shock
Moisture Resistance
Moisture Sensitivity
Resistance to Soldering Heat
MIL-STD-883, Method 3015, Class 1, HBM: 1500V
MIL-STD-883, Method 1014, Condition A
UL94-V0
MIL-STD-883, Method 1014, Condition C
MIL-STD-883, Method 2002, Condition B
MIL-STD-883, Method 1004
J-STD-020, MSL 1
MIL-STD-202, Method 210, Condition K
www.ecliptek.com | Specification Subject to Change Without Notice | Revision C 01/18/2019 | Page 1 of 7
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
EQRA14E2H-18.33111M
ENVIRONMENTAL & MECHANICAL SPECIFICATIONS CONTINUED
Resistance to Solvents
Solderability
Temperature Cycling
Vibration
MIL-STD-202, Method 215
MIL-STD-883, Method 2003
MIL-STD-883, Method 1010, Condition B
MIL-STD-883, Method 2007, Condition A
www.ecliptek.com | Specification Subject to Change Without Notice | Revision C 01/18/2019 | Page 2 of 7
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
EQRA14E2H-18.33111M
MECHANICAL DIMENSIONS (all dimensions in millimeters)
PIN
1
CONNECTION
Output Enable (OE)
Do Not Connect
Case/Ground
Output
Do Not Connect
Supply Voltage
1.70
MAX
5.00
±0.20
MARKING
ORIENTATION
2.60 ±0.15
1.2 ±0.2
2.54
TYP
5.08
±0.15
6
5
4
1
2
3
1.4 ±0.2
2
3
4
5
6
7.00
±0.20
LINE MARKING
1
2
3
ECLIPTEK
18.331M
XXXXX
XXXXX=Ecliptek
Manufacturing Identifier
Seam Sealed
Terminal Plating Thickness:
Gold (0.3 to 1.0µm) over Nickel (1.27 to 8.89µm).
Suggested Solder Pad Layout
All Dimensions in Millimeters
1.80 (X6)
2.00 (X6)
0.54 (X4)
1.89
All Tolerances are ±0.1
Solder Land
(X6)
www.ecliptek.com | Specification Subject to Change Without Notice | Revision C 01/18/2019 | Page 3 of 7
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
EQRA14E2H-18.33111M
Test Circuit for CMOS Output
Oscilloscope
Frequency
Counter
Current
Meter
Power
Supply
Voltage
Meter
0.01µF
(Note 1)
Supply
Voltage Do No
(V
DD
) Connect
Output
0.1µF
Output
(Note 1)
Enable
Do Not
Connect
Ground
Probe
(Note 2)
C
L
(Note 3)
Switch
Note 1: An external 0.01µF ceramic bypass capacitor in parallel with a 0.1µF high
frequency ceramic bypass capacitor close (less than 2mm) to the package
ground and supply voltage pin is required.
Note 2: A low capacitance (<12pF), 10X attenuation factor, high impedance
(>10Mohms), and high bandwidth (>300MHz) passive probe is recommended.
Note 3: Capacitance value C
L
includes sum of all probe and fixture capacitance.
Power
Supply
www.ecliptek.com | Specification Subject to Change Without Notice | Revision C 01/18/2019 | Page 5 of 7
Ecliptek, LLC
5458 Louie Lane, Reno, NV 89511
1-800-ECLIPTEK or 714.433.1200
stm32/stm8
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