M59PW1282
128Mbit (two 64Mb, x16, Uniform Block, LightFlash™)
3V Supply, Multiple Memory Product
FEATURES SUMMARY
■
MASK-ROM PIN-OUT COMPATIBLE
■
Figure 1. Package
TWO 64 Mbit LightFlash™ MEMORIES
STACKED IN A SINGLE PACKAGE
SUPPLY VOLTAGE
– V
CC
= 2.7 to 3.6V for Read
– V
PP
= 11.4 to 12.6V for Program and Erase
■
■
ACCESS TIME
– 90ns at V
CC
= 3.0 to 3.6V
– 100, 120ns at V
CC
= 2.7 to 3.6V
PROGRAMMING TIME
– 9µs per Word typical
– Multiple Word Programming Option
(16s typical Chip Program)
SO44 (M)
■
■
ERASE TIME
– 85s typical Chip Erase
UNIFORM BLOCKS
– 64 blocks of 2 Mbits
PROGRAM/ERASE CONTROLLER
– Embedded Word Program algorithms
10,000 PROGRAM/ERASE CYCLES per
BLOCK
ELECTRONIC SIGNATURE
– Manufacturer Code: 0020h
– Device Code : 88A8h
■
■
■
■
November 2003
1/24
M59PW1282
TABLE OF CONTENTS
SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. SO Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 2. Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Address Inputs (A0-A21) . . . . . . . . . . . . . . .
Data Inputs/Outputs (DQ0-DQ7). . . . . . . . .
Data Inputs/Outputs (DQ8-DQ15). . . . . . . .
Chip Enable (E). . . . . . . . . . . . . . . . . . . . . .
Output Enable (G). . . . . . . . . . . . . . . . . . . .
V
CC
Supply Voltage. . . . . . . . . . . . . . . . . . .
Address/Voltage Supply (A22/V
PP)
. . . . . . .
Vss Ground.. . . . . . . . . . . . . . . . . . . . . . . . .
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BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bus Read. . . . . . . . . . . . . .
Bus Write. . . . . . . . . . . . . .
Output Disable. . . . . . . . . .
Standby. . . . . . . . . . . . . . .
Automatic Standby. . . . . . .
Electronic Signature. . . . . .
Table 3. Bus Operations . .
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COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Read/Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Word Program Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Multiple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Setup Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Program Phase.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Verify Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Exit Phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Block Erase Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 4. Standard Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5. Multiple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 6. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 11
Figure 4. A22 Latch Procedure Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 7. A22 Latch Procedure AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. Programming Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. Chip Erase Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. Multiple Word Program Flowchart for 64Mbit Top and Bottom Die . . . . . . . . . . . . . . . . . 13
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M59PW1282
STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V
PP
Status Bit (DQ4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Multiple Word Program Bit (DQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Status Register Bit DQ1 is reserved.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 8. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 8. Data Polling Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 9. Data Toggle Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 9. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 10. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 10. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 11. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 12. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 13. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 13. Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 14. Chip Enable Controlled, Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 15. SO44 - 44 lead Plastic Small Outline, 500 mils body width, Package Mechanical Data . 21
Figure 14. SO44 - 44 lead Plastic Small Outline, 500 mils body width, Package Outline . . . . . . . . 21
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 16. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 17. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3/24
M59PW1282
SUMMARY DESCRIPTION
The M59PW1282 is a 128Mbit (8Mb x16), Mask-
ROM pinout compatible, non-volatile LightFlash™
memory, that can be read, erased and repro-
grammed. Read operations can be performed us-
ing a single low voltage (2.7 to 3.6V) supply.
Program and Erase operations require an addi-
tional V
PP
(11.4 to 12.6V) power supply. On pow-
er-up the memory defaults to its Read mode where
it can be read in the same way as a ROM or
EPROM.
The Mask-ROM compatibility is obtained using a
dual function Address/Voltage Supply pin (A22/
V
PP
). In Read mode the A22/V
PP
pin works as an
address pin; in Program or Erase mode it also
works as a voltage supply pin. At the beginning of
any program or erase operation, a specific proce-
dure (see Figure 4) must be performed to internal-
ly memorize the A22 value that will be used during
the program or erase operation.
The device is composed of two 64Mbit memories
stacked in a single package. Recommended oper-
ating conditions do not allow both memories to be
active at the same time. Address A22 selects the
memory to be enabled. The other memory is in
Standby mode.
The memory is divided into 64 uniform blocks that
can be erased independently so it is possible to
preserve valid data while old data is erased. Pro-
gram and Erase commands are written to the
Command Interface of the memory. An on-chip
Program/Erase Controller (P/E.C.) simplifies the
process of programming or erasing the memory by
taking care of all of the special operations that are
required to update the memory contents.
The M59PW1282 features an innovative com-
mand, Multiple Word Program, that is used to pro-
gram large streams of data. It greatly reduces the
total programming time when a large number of
Words are written to the memory at any one time.
Using this command the entire memory can be
programmed in 16s, compared to 72s using the
standard Word Program.
The end of a Program or Erase operation can be
detected and any error conditions identified. The
command set required to control the memory is
consistent with JEDEC standards. Chip Enable
and Output Enable signals control the bus opera-
tion of the memory. They allow simple connection
to most microprocessors, often without additional
logic.
The memory is offered in SO44 package and is
supplied with all the bits set to ’1’).
Figure 2. Logic Diagram
Table 1. Signal Names
A0-A21
Address Inputs
Address Input/Supply Voltage for
Program/Erase
Data Inputs/Outputs
Chip Enable
Output Enable
Supply Voltage read
Ground
VCC A22/VPP
A22/V
PP
DQ0-DQ15
22
A0-A21
16
DQ0-DQ15
E
G
E
G
M59PW1282
V
CC
V
SS
VSS
AI07209
4/24
M59PW1282
Figure 3. SO Connections
A21
A18
A17
A7
A6
A5
A4
A3
A2
A1
A0
E
VSS
G
DQ0
DQ8
DQ1
DQ9
DQ2
DQ10
DQ3
DQ11
1
44
2
43
3
42
4
41
5
40
6
39
7
38
8
37
9
36
10
35
11 M59PW1282 34
12
33
13
32
14
31
15
30
16
29
28
17
27
18
26
19
25
20
21
24
22
23
A20
A19
A8
A9
A10
A11
A12
A13
A14
A15
A16
A22/VPP
VSS
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
AI07208
5/24
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