TPS7A7200-EP
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SBVS224A – JUNE 2013 – REVISED JUNE 2013
2-A, FAST-TRANSIENT, LOW-DROPOUT VOLTAGE REGULATOR
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TPS7A7200-EP
1
FEATURES
SUPPORTS DEFENSE, AEROSPACE,
AND MEDICAL APPLICATIONS
•
•
•
•
•
•
•
Controlled Baseline
One Assembly and Test Site
One Fabrication Site
Available in Extended (–40°C to 125°C)
Temperature Range
Extended Product Life Cycle
Extended Product-Change Notification
Product Traceability
1.5 V
IN
C
IN
TPS7A7200
EN
SS
C
SS
Optional
GND
50mV
100mV
1.6V
OUT
SNS
FB
C
FF
1.2 V = 0.5 V
ref
+ 100 mV
C
OUT
+ 200 mV
+ 400 mV
PG
• Low Dropout Voltage: 180 mV at 2 A
• V
IN
Range: 1.5 V to 6.5 V
• Configurable Fixed V
OUT
Range: 0.9 V to 3.5 V
Adjustable V
OUT
Range: 0.9 V to 5.0 V
• Very Good Load and Line Transient Response
• Stable with Ceramic Output Capacitor
• 1.5% Accuracy over Line, Load, and
Temperature
• Programmable Soft-Start
• Power Good (PG) Output
• 5-mm × 5-mm QFN-20 Package
234
APPLICATIONS
•
•
•
•
•
•
Wireless Infrastructure: SerDes, FPGA, DSP™
RF Components: VCO, ADC, DAC, LVDS
Set-Top Boxes: Amplifier, ADC, DAC, FPGA,
DSP
Wireless LAN, Bluetooth
®
PCs and Printers
Audio and Visual
200mV 400mV 800mV
Typical Application
DESCRIPTION
The TPS7A7200 low-dropout (LDO) voltage regulator is designed for applications seeking very-low dropout
capability (180 mV at 2 A) with an input voltage from 1.5 V to 6.5 V. The TPS7A7200 offers an innovative, user-
configurable, output-voltage setting from 0.9 V to 3.5 V, eliminating external resistors and any associated error.
The TPS7A7200 has very fast load-transient response, is stable with ceramic output capacitors, and supports a
better than 2% accuracy over line, load, and temperature. A soft-start pin allows for an application to reduce
inrush into the load. Additionally, an open-drain, power-good signal allows for sequencing power rails.
The TPS7A7200 is available in a 5-mm × 5-mm, 20-pin QFN package.
1
2
3
4
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DSP is a trademark of Texas Instruments.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
All other trademarks are the property of their respective owners.
Copyright © 2013, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS7A7200-EP
SBVS224A – JUNE 2013 – REVISED JUNE 2013
www.ti.com
6
5.5V to 5.0V
5
Output Voltage (V)
4
3
2
1
1.5V to 1.2V
0
Time (100µs/div)
1.5V to 1.0V
Output Current
Output Current Slew Rate: 1A/µs
3
2
3.0V to 2.5V
1.8V to 1.5V
1
0
G311
Load Transient Response with
Seven Different Results:
1.5 V
IN
to 1.0 V
OUT
, 1.5 V
IN
to 1.2 V
OUT
,
1.8 V
IN
to 1.5 V
OUT
, 2.5 V
IN
to 1.8 V
OUT
,
3.0 V
IN
to 2.5 V
OUT
, 3.3 V
IN
to 3.0 V
OUT
,
and 5.5 V
IN
to 5.0 V
OUT
2
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TPS7A7200-EP
Copyright © 2013, Texas Instruments Incorporated
Output Current (A)
3.3V to 3.0V
2.5V to 1.8V
TPS7A7200-EP
www.ti.com
SBVS224A – JUNE 2013 – REVISED JUNE 2013
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
(1)
T
J
–40°C to 125°C
(1)
PACKAGE
QFN (RGW)
ORDERABLE PART NUMBER
TPS7A7200QRGWREP
TOP-SIDE MARKING
SJK
VID NUMBER
V62/13612-01XE
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
website at
www.ti.com.
ABSOLUTE MAXIMUM RATINGS
(1)
Over operating free-air temperature range (unless otherwise noted).
VALUE
MIN
IN, PG, EN
Voltage
SS, FB, SNS, OUT
50mV, 100mV, 200mV, 400mV, 800mV, 1.6V
Current
Temperature
Electrostatic Discharge Rating
(3)
(1)
(2)
(3)
OUT
PG (sink current into IC)
Junction, T
J
Storage, T
stg
Human body model (HBM, JESD22-A114A)
Charged device model (CDM, JESD22-C101B.01)
–40
–40
–0.3
–0.3
–0.3
MAX
+7.0
V
IN
+ 0.3
(2)
UNIT
V
V
V
A
mA
V
OUT
+ 0.3
5
+150
+150
2
500
Internally limited
°C
kV
V
Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
The absolute maximum rating is V
IN
+ 0.3 V or +7.0 V, whichever is smaller.
ESD testing is performed according to the respective JESD22 JEDEC standard.
THERMAL INFORMATION
TPS7A7200-EP
THERMAL METRIC
(1)
θ
JA
θ
JCtop
θ
JB
ψ
JT
ψ
JB
θ
JCbot
Junction-to-ambient thermal resistance
(2)
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
(4)
(3)
RGW
20 PINS
35.7
33.6
15.2
0.4
15.4
3.8
UNITS
Junction-to-top characterization parameter
(5)
Junction-to-board characterization parameter
(6)
Junction-to-case (bottom) thermal resistance
(7)
°C/W
(1)
(2)
(3)
(4)
(5)
(6)
(7)
For more information about traditional and new thermal metrics, see the
IC Package Thermal Metrics
application report,
SPRA953.
The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
The junction-to-top characterization parameter,
ψ
JT
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-board characterization parameter,
ψ
JB
, estimates the junction temperature of a device in a real system and is extracted
from the simulation data for obtaining
θ
JA
, using a procedure described in JESD51-2a (sections 6 and 7).
The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
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Copyright © 2013, Texas Instruments Incorporated
TPS7A7200-EP
SBVS224A – JUNE 2013 – REVISED JUNE 2013
www.ti.com
ELECTRICAL CHARACTERISTICS
Over operating temperature range (T
J
= –40°C to +125°C), 1.425 V
≤
V
IN
≤
6.5 V, V
IN
≥
V
OUT(TARGET)
+ 0.3 V or
V
IN
≥
V
OUT(TARGET)
+ 0.5 V
(1) (2)
, OUT connected to 50
Ω
to GND
(3)
,V
EN
= 1.1 V, C
OUT
= 10
μF,
C
SS
= 10 nF, C
FF
= 0 pF
(4)
, and
PG pin pulled up to V
IN
with 100 kΩ, 27 kΩ
≤
R2
≤
33 kΩ for adjustable configuration
(5)
, unless otherwise noted.
Typical values are at T
J
= +25°C.
PARAMETER
V
IN
V
(SS)
Input voltage range
SS pin voltage
Output voltage range
V
OUT
Output voltage accuracy
(6) (7)
Adjustable with external feedback resistors
Fixed with voltage setting pins
Adjustable, 25 mA
≤
I
OUT
≤
2 A
Fixed, 25 mA
≤
I
OUT
≤
2 A
ΔV
O(ΔVI)
ΔV
O(ΔIO)
V
(DO)
I
(LIM)
Line regulation
Load regulation
Dropout voltage
(8)
TEST CONDITIONS
MIN
1.425
TYP
MAX
6.5
UNIT
V
V
0.5
0.9
0.9
–2.0
–3.0
0.01
0.1
180
470
2.4
3.1
2.6
4
0.1
5
±0.1
0
1.1
For the direction PG↓ with decreasing V
OUT
For PG↑
V
OUT
< V
IT(PG)
, I
PG
= –1 mA (current into device)
V
OUT
> V
IT(PG)
, V
(PG)
= 6.5 V
V
(SS)
= GND, V
IN
= 3.3 V
BW = 100 Hz to 100 kHz,
V
IN
= 1.5 V, V
OUT
= 1.2 V, I
OUT
= 2 A
Shutdown, temperature increasing
Reset, temperature decreasing
–40
3.5
5.1
40.65
+160
+140
+125
0.85V
OUT
0.9V
OUT
0.02V
OUT
0.4
1
7.2
0.5
6.5
0.96V
OUT
5.0
3.5
+2.0
+3.0
V
%
I
OUT
= 25 mA
25 mA
≤
I
OUT
≤
2 A
V
OUT
≤
3.3 V, I
OUT
= 2 A, V
(FB)
= GND
3.3 V < V
OUT
, I
OUT
= 2 A, V
(FB)
= GND
V
OUT
forced at 0.9 × V
OUT(TARGET)
, V
IN
= 3.3 V,
V
OUT(TARGET)
= 0.9 V
Full load, I
OUT
= 2 A
Minimum load,
V
IN
= 6.5 V, V
OUT(TARGET)
= 0.9 V, I
OUT
= 25 mA
Shutdown, PG = (open),
V
IN
= 6.5 V, V
OUT(TARGET)
= 0.9 V, V
(EN)
< 0.5 V
%/V
%/A
mV
mV
A
mA
mA
μA
μA
V
V
V
V
V
μA
μA
μV
RMS
°C
°C
°C
Output current limit
I
(GND)
GND pin current
I
(EN)
V
IL(EN)
V
IH(EN)
V
IT(PG)
V
hys(PG)
V
OL(PG)
I
lkg(PG)
I
(SS)
V
n
T
sd
T
J
EN pin current
EN pin low-level input voltage
(disable device)
EN pin high-level input voltage
(enable device)
PG pin threshold
PG pin hysteresis
PG pin low-level output voltage
PG pin leakage current
SS pin charging current
Output noise voltage
Thermal shutdown temperature
Operating junction temperature
V
IN
= 6.5 V, V
(EN)
= 0 V and 6.5 V
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
When V
OUT
≤
3.5 V, V
IN
≥
(V
OUT
+ 0.3 V) or 1.425 V, whichever is greater; when V
OUT
> 3.5 V, V
IN
≥
(V
OUT
+ 0.5 V).
V
OUT(TARGET)
is the calculated target V
OUT
value from the output voltage setting pins: 50mV, 100mV, 200mV, 400mV, 800mV, and 1.6V
in fixed configuration, or the expected V
OUT
value set by external feedback resistors in adjustable configuration.
This 50-Ω load is disconnected when the test conditions specify an I
OUT
value.
C
FF
is the capacitor between FB pin and OUT
R2 is the bottom-side of the feedback resistor between the FB pin and OUT. See
Figure 40
for details.
When the TPS7A7200 is connected to external feedback resistors at the FB pin, external resistor tolerances are not included.
The TPS7A7200 is not tested at V
OUT
= 0.9 V, 2.7 V
≤
V
IN
≤
6.5 V, and 500 mA
≤
I
OUT
≤
2 A because the power dissipation is higher
than the maximum rating of the package. Also, this accuracy specification does not apply on any application condition that exceeds the
power dissipation limit of the package.
V
(DO)
is not defined for output voltage settings below 1.2 V.
4
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TPS7A7200-EP
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TPS7A7200-EP
www.ti.com
SBVS224A – JUNE 2013 – REVISED JUNE 2013
FUNCTIONAL BLOCK DIAGRAM
IN
Charge
Pump
Current
Limit
UVLO
OUT
Thermal
Protection
PG
SS
C
SS
0.5-V Reference
1.2-V Reference
70 kΩ
700-µs
Delay
0.45 V
50 kΩ
SNS
32R
FB
Optional
50 kΩ
EN
Hysteresis
320R
160R
80R
40R
20R
10R
GND
50mV
100mV 200mV 400mV 800mV
1.6V
NOTE: 320R = 1.024 MΩ (that is, 1R = 3.2 kΩ).
Figure 1. Functional Block Diagram
Copyright © 2013, Texas Instruments Incorporated
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