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TPS61280D
SLVSEA0A – JANUARY 2018 – REVISED AUGUST 2018
TPS6128xD Low-IQ, Wide-Voltage Battery Front-End DC/DC Converter for
Single-Cell Li-Ion, Ni-Rich, Si-Anode Applications
1 Features
•
•
1
3 Description
The TPS6128xD device provides a power supply
solution for products powered by either by a Li-Ion,
Nickel-Rich, Silicon Anode, Li-Ion or LiFePO4 battery.
The voltage range is optimized for single-cell portable
applications like in smart-phones or tablet PCs.
Used as a high-power pre-regulator, the TPS6128xD
extends the battery run-time and overcomes input
current- and voltage limitations of the powered
system.
While in shutdown, the TPS6128xD operates in a true
pass-through mode with only 3-µA quiescent
consumption for longest battery shelf life.
During operation, when the battery is at a good state-
of-charge, a low-ohmic, high-efficient integrated pass-
through path connects the battery to the powered
system.
If the battery gets to a lower state of charge and its
voltage becomes lower than the desired minimum
system voltage, the device seamlessly transits into
boost mode to uses the full battery capacity.
Device Information
(1)
PART NUMBER
TPS61280D
TPS61281D
TPS61282D
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
DSBGA (16)
1.66 mm x 1.66 mm
PACKAGE
BODY SIZE (NOM)
•
•
•
•
•
•
•
•
•
•
•
95% Efficiency at 2.3 MHz Operation
3-µA Quiescent Current in Low I
Q
Pass-Through
Mode
Wide V
IN
Range From 2.3 V To 4.8 V
I
OUT
≥
4A (Peak) at V
OUT
= 3.35 V, V
IN
≥
2.65 V
Integrated Pass-Through Mode (35 mΩ)
Programmable Valley Inductor Current Limit and
Output Voltage
True Pass-Through Mode During Shutdown
Best-in-Class
Line and Load Transient
Low-Ripple Light-Load PFM Mode
In-Situ Customization with On-Chip E
2
PROM
(Write Protection)
Two Interface Options:
– I
2
C Compatible I/F up to 3.4 Mbps
(TPS61280D)
– Simple I/O Logic Control Interface
Thermal Shutdown and Overload Protection
Total Solution Size < 20 mm
2
, Sub 1-mm Profile
2 Applications
•
•
•
Single-Cell Ni-Rich, Si-Anode, Li-Ion, LiFePO4
Smart-Phones or Tablet PCs
2.5G, 3G, 4G Mini-Module Data Cards
Current Limited Applications Featuring High Peak
Power Loads
Simplified Schematic
TPS61280D
SW
VOUT
VOUT
VBAT’
L
SW
0.47
μ
H
VIN
C
O
(x2)
10µF X5R 6.3V (0603)
Battery
2.5V .. 4.35V
VIN
C
I
1.5µF X5R 6.3V (0402)
Voltage Select
Enable
Forced Bypass / Auto
VSEL
EN
BYP
SCL
1.8V
I C Bus
2
SDA
PGND
PGND
PGND
GPIO
Interrupt
AGND
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS61280D
SLVSEA0A – JANUARY 2018 – REVISED AUGUST 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features
..................................................................
Applications
...........................................................
Description
.............................................................
Revision History.....................................................
Description (continued).........................................
Device Comparison Table.....................................
Pin Configuration and Functions
.........................
Specifications.........................................................
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
1
1
1
2
3
3
4
6
9.4 Device Functional Modes........................................
17
9.5 Programming...........................................................
22
9.6 Register Maps .........................................................
25
10 Application and Implementation........................
33
10.1 Application Information..........................................
33
10.2 Typical Application ................................................
34
11 Power Supply Recommendations
.....................
46
12 Layout...................................................................
46
12.1 Layout Guidelines .................................................
46
12.2 Layout Example ....................................................
46
12.3 Thermal Information ..............................................
47
Absolute Maximum Ratings .....................................
6
ESD Ratings..............................................................
6
Recommended Operating Conditions.......................
6
Thermal Information ..................................................
7
Electrical Characteristics...........................................
7
I
2
C Interface Timing Characteristics ........................
9
I
2
C Timing Diagrams...............................................
11
Typical Characteristics ............................................
12
13 Device and Documentation Support
.................
48
13.1
13.2
13.3
13.4
13.5
13.6
Device Support......................................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
48
48
48
48
48
48
9
Detailed Description
............................................
14
9.1 Overview .................................................................
14
9.2 Functional Block Diagram .......................................
15
9.3 Feature Description.................................................
16
14 Mechanical, Packaging, and Orderable
Information
...........................................................
49
14.1 Package Summary................................................
49
4 Revision History
Changes from Original (January 2018) to Revision A
•
•
•
Page
Changed devices TPS61281D and TPS61282D From:
Product Preview
To:
Production
data .............................................
1
Changed the TPS61280D pin configuration ...........................................................................................................................
4
Changed the TPS6128xD pin configuration ...........................................................................................................................
5
2
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Product Folder Links:
TPS61280D
Copyright © 2018, Texas Instruments Incorporated
TPS61280D
www.ti.com
SLVSEA0A – JANUARY 2018 – REVISED AUGUST 2018
5 Description (continued)
TPS6128xD device supports more than 4 A pulsed load current even from a deeply discharged battery. In this
mode of operation, the TPS6128xD enables the use of the full battery capacity: A high battery-cut-off voltage
originated by powered components with a high minimum input voltage is overcome; new battery chemistries can
be fully discharged; high current pulses forcing the system into shutdown are buffered by the device seamlessly
transitioning between boost and by-pass mode back and forth.
This has significant impact on the battery on-time and translates into either a longer use-time and better user-
experience at an equal battery capacity or into reduced battery costs at similar use-times.
The TPS6128xD offers a small solution size (< 20 mm
2
) due to minimum amount of external components,
enabling the use of small inductors and input capacitors, available as a 16-pin chip-scale package (CSP).
The TPS6128xD operates in synchronous, 2.3 MHz boost mode and enters power-save mode operation (PFM)
at light load currents to maintain high efficiency over the entire load current range.
6 Device Comparison Table
PART NUMBER
I
2
C Control Interface
User Prog. E
2
PROM Settings
DEVICE
SPECIFIC FEATURES
DC/DC boost / bypass threshold = 3.15 V (VSEL = L)
DC/DC boost / bypass threshold = 3.35 V (VSEL = H)
Valley inductor current limit = 3 A
DC/DC boost / bypass threshold = 3.15 V (VSEL = L)
TPS61281D
Simple Logic Control Interface
DC/DC boost / bypass threshold = 3.35 V (VSEL = H)
Valley inductor current limit = 3 A
DC/DC boost / bypass threshold = 3.3 V (VSEL = L)
TPS61282D
Simple Logic Control Interface
DC/DC boost / bypass threshold = 3.5 V (VSEL = H)
Valley inductor current limit = 4 A
TPS61280D
Copyright © 2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
TPS61280D
3
TPS61280D
SLVSEA0A – JANUARY 2018 – REVISED AUGUST 2018
www.ti.com
7 Pin Configuration and Functions
TPS61280D YFF Package
16-Bump DSBGA
Top View
1
2
3
4
1
2
3
4
TPS61280D YFF Package
16-Bump DSBGA
Bottom View
A
EN
GPIO
VIN
VIN
D
AGND
PGND
PGND
PGND
B
VSEL
SCL
VOUT
VOUT
C
nBYP
SDA
SW
SW
C
nBYP
SDA
SW
SW
B
VSEL
SCL
VOUT
VOUT
D
AGND
PGND
PGND
PGND
A
EN
GPIO
VIN
VIN
Not to scale
Not to scale
Pin Functions, TPS61280D
PIN
NAME
VIN
VOUT
NO.
A3, A4
B3, B4
I/O
I
O
Power supply input.
Boost converter output.
This is the enable pin of the device. On the rising edge of the enable pin, all the registers are reset with their default
values. This input must not be left floating and must be terminated.
EN = Low: The device is forced into shutdown mode and the I2C control interface is disabled. Depending on the
logic level applied to the nBYP input, the converter can either be forced in pass-through mode or it's output can be
regulated to a minimum level so as to limit the input-to-output voltage difference to less than 3.6V (typ). The current
consumption is reduced to a few µA. For more details, refer to
Table 2.
EN = High: The device is operating normally featuring automatic dc/dc boost, pass-through mode transition. For
more details, refer to
Table 2.
This pin can either be configured as a input (mode selection) or as dual role input/open-drain output RST/FAULT )
pin. Per default, the pin is configured as RST/FAULT input/output. The input must not be left floating and must be
terminated.
Manual Reset Input: Drive RST/FAULT low to initiate a reset of the converter's output. nRST/nFAULT controls a
falling edge-triggered sequence consisting of a discharge phase of the capacitance located at the converter's output
followed by a start-up phase.
GPIO
A2
I/O
Fault Output (open-drain interrupt signal to host): Indicates that a fault has occurred (e.g. thermal shutdown, output
voltage out of limits, current limit triggered, and so on). To signal such an event, the device generates a falling edge-
triggered interrupt by driving a negative pulse onto the GPIO line and then releases the line to its inactive state.
Mode selection input = Low: The device is operating in regulated frequency pulse width modulation mode (PWM) at
high-load currents and in pulse frequency modulation mode (PFM) at light load currents.
Mode selection input = High: Low-noise mode enabled, regulated frequency PWM operation forced.
VSEL
nBYP
SCL
SDA
SW
PGND
AGND
B1
C1
B2
C2
C3, C4
D2, D3, D4
D1
I
I
I
I/O
I/O
VSEL signal is primarily used to set the output voltage dc/dc boost, pass-through threshold. This pin must not be left
floating and must be terminated.
A logic low level on the BYP input forces the device in pass-through mode. This pin must not be left floating and
must be terminated.
Serial interface clock line. This pin must not be left floating and must be terminated.
Serial interface address/data line. This pin must not be left floating and must be terminated.
Inductor connection. Drain of the internal power MOSFET. Connect to the switched side of the inductor.
Power ground pin.
Analog ground pin. This is the signal ground reference for the IC.
DESCRIPTION
EN
A1
I
4
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Product Folder Links:
TPS61280D
Copyright © 2018, Texas Instruments Incorporated
TPS61280D
www.ti.com
SLVSEA0A – JANUARY 2018 – REVISED AUGUST 2018
TPS6128xD YFF Package
16-Bump DSBGA
Top View
1
2
3
4
1
A
EN
PG
VIN
VIN
D
TPS6128xD YFF Package
16-Bump DSBGA
Bottom View
2
3
4
AGND
PGND
PGND
PGND
B
VSEL
MODE
VOUT
VOUT
C
nBYP
AGND
SW
SW
C
nBYP
AGND
SW
SW
B
VSEL
MODE
VOUT
VOUT
D
AGND
PGND
PGND
PGND
A
Not to scale
Not to scale
EN
PG
VIN
VIN
Pin Functions, TPS6128xD
PIN
NAME
VIN
VOUT
NO.
A3, A4
B3, B4
I/O
I
O
Power supply input.
Boost converter output.
This is the enable pin of the device. On the rising edge of the enable pin, all the registers are reset with their default
values. This input must not be left floating and must be terminated.
EN = Low: The device is forced into shutdown mode. Depending on the logic level applied to the nBYP input, the
converter can either be forced in pass-through mode or it's output can be regulated to a minimum level so as to limit
the input-to-output voltage difference to less than 3.6V (typ). The current consumption is reduced to a few µA. For
more details, refer to
Table 2.
EN = High: The device is operating normally featuring automatic dc/dc boost, pass-through mode transition. For
more details, refer to
Table 2.
Power-Good Output (open-drain output to host): A logic high on the PG output indicates that the converter's output
voltage is within its regulation limits. A logic low indicates a fault has occurred (e.g. thermal shutdown, output voltage
out of limits, current limit triggered, and so on). The PG signal is de-asserted automatically once the IC resumes
proper operation.
VSEL signal is primarily used to set the output voltage dc/dc boost, pass-through threshold. This pin must not be left
floating and must be terminated.
A logic low level on the BYP input forces the device in pass-through mode. For more details, refer to
Table 2.
This
pin must not be left floating and must be terminated.
This is the mode selection pin of the device. This pin must not be left floating, must be terminated and can be
connected to AGND. During start-up this pin must be held low. Once the output voltage settled and PG pin indicates
that the converter's output voltage is within its regulation limits the device can be forced in PWM mode operation by
applying a high level on this pin.
MODE
B2
I
MODE = Low: The device is operating in regulated frequency pulse width modulation mode (PWM) at high-load
currents and in pulse frequency modulation mode (PFM) at light load currents. This pin must be held low during
device start-up.
MODE = High: Low-noise mode enabled, regulated frequency PWM operation forced.
SW
PGND
AGND
C3, C4
D2, D3, D4
C2, D1
I/O
Inductor connection. Drain of the internal power MOSFET. Connect to the switched side of the inductor.
Power ground pin.
Analog ground pin. This is the signal ground reference for the IC.
DESCRIPTION
EN
A1
I
PG
A2
O
VSEL
nBYP
B1
C1
I
I
Copyright © 2018, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links:
TPS61280D
5
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