SN75C189, SN75C189A
QUADRUPLE LOW-POWER LINE RECEIVERS
SLLS041G – OCTOBER 1988 – REVISED JANUARY 2000
D
D
D
D
D
D
D
D
Meet or Exceed the Requirements of
TIA/EIA-232-F and ITU Recommendation
V.28
Low Supply Current
. . .
420
µA
Typ
Preset On-Chip Input Noise Filter
Built-in Input Hysteresis
Response and Threshold Control Inputs
Push-Pull Outputs
Functionally Interchangeable and
Pin-to-Pin Compatible With
Texas Instruments SN75189/SN75189A and
Motorola MC1489/MC1489A
Package Options Include Plastic
Small-Outline (D) and Shrink Small-Outline
(DB) Packages, and Standard Plastic (N)
DIP
D, DB, OR N PACKAGE
(TOP VIEW)
1A
1 CONT
1Y
2A
2 CONT
2Y
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
4A
4 CONT
4Y
3A
3 CONT
3Y
description
The SN75C189 and SN75C189A are low-power, bipolar, quadruple line receivers that are used to interface data
terminal equipment (DTE) with data circuit-terminating equipment (DCE). These devices have been designed
to conform to TIA/EIA-232-F.
The SN75C189 has a 0.33-V typical hysteresis, compared with 0.97 V for the SN75C189A. Each receiver has
provision for adjustment of the overall input threshold levels. This is achieved by choosing external series
resistors and voltages to provide bias levels for the response-control pins. The output is in the high logic state
if the input is open circuit or shorted to ground.
These devices have an on-chip filter that rejects input pulses of less than 1-µs duration. An external capacitor
can be connected from the control pins to ground to provide further input noise filtering for each receiver.
The SN75C189 and SN75C189A have been designed using low-power techniques in a bipolar technology. In
most applications, these receivers interface to single inputs of peripheral devices such as UARTs, ACEs, or
microprocessors. By using sampling, such peripheral devices usually are insensitive to the transition times of
the input signals. If this is not the case, or for other uses, it is recommended that the SN75C189 and SN75C189A
outputs be buffered by single Schmitt input gates or single gates of the HCMOS, ALS, or 74F logic families.
The SN75C189 and SN75C189A are characterized for operation from 0°C to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
©
2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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SN75C189, SN75C189A
QUADRUPLE LOW-POWER LINE RECEIVERS
SLLS041G – OCTOBER 1988 – REVISED JANUARY 2000
logic symbol
†
1A
1 CONT
2A
2 CONT
3A
3 CONT
4A
4 CONT
1
2
4
5
10
9
13
12
11
4Y
8
THRESHOLD
ADJUST
3
1Y
logic diagram (each receiver)
A
Response
Control
Y
6
2Y
3Y
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
schematic of inputs and outputs
EQUIVALENT OF EACH INPUT
‡
Input
3.4 kΩ
Response
Control
ESD
Protection
1.5 kΩ
ESD
Protection
Output
EQUIVALENT OF EACH OUTPUT
VCC
530
Ω
‡ All resistor values shown are nominal.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
§
Supply voltage, V
CC
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
Input voltage range, V
I
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 V to 30 V
Output voltage range, V
O
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to V
CC
+ 0.3 V
Package thermal impedance,
θ
JA
(see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
§ Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to network GND.
2. The package thermal impedance is calculated in accordance with JESD 51.
2
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SN75C189, SN75C189A
QUADRUPLE LOW-POWER LINE RECEIVERS
SLLS041G – OCTOBER 1988 – REVISED JANUARY 2000
recommended operating conditions
MIN
VCC
VI
IOH
IOL
Supply voltage
Input voltage (see Note 3)
High-level output current
Low-level output current
Response-control current
4.5
–25
NOM
5
MAX
6
25
–3.2
3.2
±1
UNIT
V
V
mA
mA
mA
TA
Operating free-air temperature
0
70
°C
NOTE 3: The algebraic convention, where the more positive (less negative) limit is designated as maximum, is used in this data sheet for logic
levels only, e.g., if –10 V is a maximum, the typical value is a more negative voltage.
electrical characteristics over recommended free-air temperature range, V
CC
= 5 V
±
10% (unless
otherwise noted) (see Note 4)
PARAMETER
VIT
IT+
VIT
IT–
Vh
hys
Positive-going
Positive going input threshold voltage
Negative-going
Negative going input threshold voltage
Input hysteresis voltage (VIT – VIT )
IT+
IT–
’C189
’C189A
’C189
’C189A
’C189
’C189A
TEST CONDITIONS
See Figure 1
See Figure 1
See Figure 1
VCC = 4.5 V to 6 V,
,
IOH = –20
µA
VCC = 4.5 V to 6 V,
IOH = –3.2 mA
VCC = 4.5 V to 6 V,
,
IOL = 3.2 mA
See Figure 2
See Figure 2
See Figure 3
VI = 5 V,
See Figure 2
No load,
420
VI = 0.75 V,
,
VI = 0.75 V,
VI = 3 V,
,
VI = 25 V
VI = 3 V
VI = –25 V
VI = –3 V
3.6
0.43
–3.6
–0.43
MIN
1
1.6
0.75
0.75
0.15
0.65
3.5
35
V
2.5
0.4
04
8.3
1
–8.3
–1
–35
700
V
mA
mA
mA
µA
1
0.33
0.97
TYP†
MAX
1.5
2.25
1.25
1.25
UNIT
V
V
V
VOH
High-level
High level output voltage
VOL
IIH
IIL
IOS
ICC
Low-level
Low level output voltage
High-level
High level input current
Low-level
Low level input current
Short-circuit output current
Supply current
† All typical values are at TA = 25°C.
NOTE 4: All characteristics are measured with response-control terminal open.
switching characteristics, V
CC
= 5 V
±
10%, T
A
= 25°C
PARAMETER
tPLH
tPHL
tTLH
tTHL
Propagation delay time, low- to high-level output
Propagation delay time, high- to low-level output
Transition time, low- to high-level output‡
Transition time, high- to low-level output‡
RL = 5 kΩ,
CL = 50 pF,
See Figure 4
TEST CONDITIONS
MIN
TYP
MAX
6
6
500
300
UNIT
µs
µs
ns
ns
tw(N)
Duration of longest pulse rejected as noise§
1
6
µs
‡ Measured between 10% and 90% points of output waveform
§ The receiver ignores any positive- or negative-going pulse that is less than the minimum value of tw(N) and accepts any postive- or negative-going
pulse greater than the maximum of tw(N).
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SN75C189, SN75C189A
QUADRUPLE LOW-POWER LINE RECEIVERS
SLLS041G – OCTOBER 1988 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC
VIT, V1
Response
Control
Open Unless
Otherwise Specified
RC
CC
–VC
RC
VC
NOTE A: Arrows indicate actual direction of current flow. Current into a terminal is a positive value.
Figure 1. V
T+
, V
IT–
, V
OH
, V
OL
VCC
IIH
–IIL
Response Control
Open
NOTE A: Arrows indicate actual direction of current flow. Current into a terminal is a positive value.
ICC
Open
VI
Figure 2. I
IH
, I
IL
, I
CC
VCC
Response Control
Open
NOTE A: Arrows indicate actual direction of current flow. Current into a terminal is a positive value.
Figure 3. I
OS
4
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ÎÎÎ Î Î
ÎÎÎ Î Î
VOH
VOL
IOL
–IOS
–IOH
SN75C189, SN75C189A
QUADRUPLE LOW-POWER LINE RECEIVERS
SLLS041G – OCTOBER 1988 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
VCC
Pulse
Generator
(see Note B)
RL = 5 kΩ
Response Control
Open
TEST CIRCUIT
3V
Input
1.5 V
1.5 V
0V
tPHL
90%
Output
tTHL
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitances.
B. The pulse generator has the following characteristics: ZO = 50
Ω,
tw = 25
µs.
tPLH
90%
1.5 V
10%
1.5 V
10%
tTLH
VOH
Output
CL = 50 pF
(see Note A)
VOL
Figure 4. Test Circuit and Voltage Waveforms
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