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April 1997
ML4880
Portable PC/PCMCIA Power Controller
GENERAL DESCRIPTION
The ML4880 Portable PC and PCMCIA Power Controller
is a complete solution for DC/DC power conversion for
portable computing systems with single or multiple
PCMCIA slots.
The device provides two synchronous buck controllers to
implement mixed voltage systems and a flyback controller
for 12V V
PP
generation for PCMCIA slots. The flyback
architecture enables generation of high currents (150mA
or more per slot) on the 12V bus for multiple slot PCMCIA
applications.
Each regulator can be independently switched off to fully
isolate the load from the power supply. The PFM
architecture will automatically adjust switching frequency
at light loads in order to maintain power conversion
efficiencies in excess of 90% over a wide output power
range.
FEATURES
s
s
Regulation to ±3% maximum: provides 2% PCMCIA
switch matrix margin
Two synchronous buck controllers for 3.3/3V, 5V
generation, and a flyback for high current, 12V
generation from 5.5V to 18V input
Regulator power conversion efficiencies > 90%
Pulse frequency modulation for high efficiency
operation
Independent regulator shutdown for full load isolation
Adjustable current limit
Wide input voltage range (5.5V to 18V)
s
s
s
s
s
BLOCK DIAGRAM
VIN
15
24
V
REG
CLAMP
GATE
CLAMP
CLAMP A
P DRV A
2
16
VIN
BUCK REGULATOR A
BIAS
CIRCUITS
13
+
N DRV A
ISENSE A
PWR GND A
23
14
4
VIN
5.5 – 18V
6
GND
VOUT A
2.5 – 3.5V
7
GND
SHDN A
SHDN B
SHDN C
SHUTDOWN
LOGIC
–
VFB A
9
TO SYSTEM
POWER
MANAGEMENT
11
18
10
VIN
CLAMP
GATE
CLAMP
CLAMP B
1
P DRV B
19
FLYBACK REGULATOR C
+
17
N DRV C
ISENSE C
BUCK REGULATOR B
+
N DRV B
ISENSE B
PWR GND B
22
20
5
3
VOUT C
6V – 15V
12
VOUT B
4.5 – 5.0V
VFB C
PWR GND C
–
VFB B
8
–
21
REV. 1.0 10/12/2000
ML4880
PIN CONFIGURATION
ML4880
24-Pin SOIC (S24)
CLAMP B
CLAMP A
I
SENSE
C
I
SENSE
A
I
SENSE
B
GND
GND
V
FB
B
V
FB
A
SHDN C
SHDN A
V
FB
C
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLAMP
PWR GND A
PWR GND B
PWR GND C
NDRV B
PDRV B
SHDN B
NDRV C
V
IN
V
REG
NDRV A
PDRV A
TOP VIEW
PIN DESCRIPTION
PIN# NAME
FUNCTION
PIN# NAME
FUNCTION
1
2
3
4
5
6
7
8
9
CLAMP B
CLAMP A
I
SENSE
C
I
SENSE
A
I
SENSE
B
GND
GND
V
FB
B
V
FB
A
Gate clamp, regulator B
Gate clamp, regulator A
Current sense, regulator C
Current sense, regulator A
Current sense, regulator B
Ground
Ground
Feedback node, buck regulator B
Feedback node, buck regulator A
Shutdown input, regulator C
Shutdown input, regulator A
Feedback node, regulator C
13 PDRV A
14 NDRV A
15 V
REG
16 V
IN
17 NDRV C
18 SHDN B
19 PDRV B
20 NDRV B
P-channel drive, regulator A
N-channel drive, regulator A
Linear regulator output
Power supply input voltage
N-channel drive, regulator C
Shutdown input, regulator B
P-channel drive, regulator B
N-channel drive, regulator B
21 PWR GND C Power Ground, regulator C
22 PWR GND B Power Ground, regulator B
23 PWR GND A Power Ground, regulator A
24 CLAMP
Charge pump capacitor input
10 SHDN C
11 SHDN A
12 V
FB
C
2
REV. 1.0 10/12/2000
ML4880
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings are those values beyond
which the device could be permanently damaged.
Absolute maximum ratings are stress ratings only and
functional device operation is not implied.
V
IN ................................................................................................
20V
Peak Driver Output Current ......................................... 2A
V
FB
Voltage ........................................ GND – 0.3V to 6V
I
SENSE
Voltage ..................................................... ±500mV
All Other Analog Inputs .......... GND – 0.3V to V
IN
+ 0.3V
All Digital Inputs ................. GND – 0.3V to V
REG
+ 0.3V
Junction Temperature ............................................ 150°C
Storage Temperature Range .................... –65°C to 150°C
Lead Temperature (Soldering, 10 sec) .................... 150°C
Thermal Resistance (θ
JA
) ...................................... 80°C/W
OPERATING CONDITIONS
V
IN
Range .................................................... 5.5V to 18V
Temperature Range
ML4880CS ................................................ 0°C to 70°C
ML4880ES ............................................. –20°C to 70°C
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, V
IN
= 14V, C(V
REG
) = 10µF, T
A
= Operating Temperature Range (Note 1)
PARAMETER
Shutdown Inputs
Input Low Voltage
Input High Voltage
Input Bias Current
Buck Regulator A
Duty Cycle Ratio
V
FB
A Threshold Voltage
I
SENSE
A Threshold Voltage
Transition Time
Buck Regulator B
Duty Cycle Ratio
V
FB
B Threshold Voltage
I
SENSE
B Threshold Voltage
Transition Time
Flyback Regulator C
Duty Cycle Ratio
V
IN
= 5.5V, I
SENSE
C = V
FB
C = 0V
V
IN
= 18V, I
SENSE
C = V
FB
C = 0V
V
FB
C Threshold Voltage
I
SENSE
C Threshold Voltage
Transition Time
Supply
Linear Regulator Output Voltage
Linear Regulator Load Regulation
V
IN
Current
7V - V
IN
- 18V
I(V
REG
) = 0 to 10mA
SHDN A/B/C = 5V
SHDN A/B/C = 0V
Note 1:
Limits are guaranteed by 100% testing, sampling or correlation with worst case test conditions.
CONDITIONS
MIN
TYP
MAX
UNITS
0.8
2.0
–1
1
V
V
µA
V
IN
= 5.5V, I
SENSE
A = V
FB
A = 0V
86
1.21
–140
1.25
–200
80
96
1.29
–250
100
%
V
mV
ns
C
L
= 1000pF, 0 to V
REG
V
IN
= 5.5V, I
SENSE
B = V
FB
B = 0V
92
1.21
–140
C
L
= 1000pF, 0 to V
REG
86
61
1.21
–140
C
L
= 1000pF, 0 to V
REG
6.25
6.10
98
1.25
–200
80
1.29
–250
100
%
V
mV
ns
94
77
1.25
–200
80
1.29
–250
100
%
%
V
mV
ns
6.99
6.99
300
350
350
400
V
V
µA
µA
REV. 1.0 10/12/2000
3
ML4880
FUNCTIONAL DESCRIPTION
The ML4880 converts a 5.5V to 18V input to three outputs
via two synchronous buck controllers and a flyback
controller. The two buck controllers utilize a unique
current mode PFM control architecture that generate
output voltages in the range of 2.5V to 3.5V (output A),
and 4.5V to 5V (output B). The output current is set by
external components, and can exceed 2A on each supply.
The flyback controller also uses a current mode PFM
control scheme and can be used to generate a 6V to 15V
output. Again, the output current of the flyback is
dependent on external components, and output currents of
500mA are obtainable. Even at light loads, the PFM
architecture maintains high conversion efficiencies over a
wide range of input voltages. If it is necessary to further
extend battery life, the user can shutdown and fully
disconnect each load from the input independently.
BIAS CIRCUITS
The bias circuits are comprised of a linear regulator and a
precision voltage reference. The linear regulator produces
a supply voltage (V
REG
) used by the control circuits. The
V
REG
pin should be bypassed to GND with a 4.7µF to
10µF capacitor. The precision voltage reference is used by
the feedback circuit of each controller to maintain an
accurate output voltage.
SHUTDOWN LOGIC
Each controller has a separate shutdown pin. By applying
a logic high to the appropriate pin, the transconductance
amplifier and current comparator of each controller
(shown in Figures 1 and 3) can be disabled. This prevents
switching from occurring and disconnects the load from
the input. All other circuitry within the ML4880 remains
active during shutdown.
GATE CLAMP
The gate clamp circuit provides a method of preventing
the buck regulator P-channel MOSFET switches from
accidentally turning on when the input is suddenly
switched to a higher voltage. This condition can occur
during start-up or when an adapter voltage is applied. As
shown in the block diagram, the P DRV drivers are
capacitively coupled to the gates.
Assume that P DRV is in the OFF state, or at V
REG
, and
the gate voltage is held at V
IN
through the resistor. The
gate-source voltage of the MOSFET is 0V and the switch
stays off. If a higher input voltage (V
IN
+ 5V for example)
is suddenly applied with P DRV still in the OFF state, the
source voltage of the MOSFET would jump up to V
IN
+
5V, but the gate would still be at V
IN
. The gate-source
voltage becomes –5V and the P-channel MOSFET would
turn on even though P DRV is still in the OFF state. In
order to prevent the MOSFET from turning on, the gate
clamp circuit senses the increase in the input voltage and
pumps charge into the gate side of the coupling capacitor,
quickly charging the capacitor to the new input voltage
level.
The CLAMP pin requires a capacitor to GND in order for
the gate clamp circuit to function properly. The capacitor
value should be 1.5 to 2 times the value used for the
coupling capacitor.
BUCK CONTROLLERS
A block diagram of the buck controllers is shown in
Figure 1. The circuit utilizes a constant ON-time PFM
control architecture. The circuit determines the OFF-time
by waiting for the inductor current to drop to a level set
by the feedback voltage (V
FB
).
V
IN
T
ON
C
IN
OSCILLATOR/
ONE SHOT
P DRV
L
SHOOT THRU
PROTECTION
V
OUT
C
OUT
N DRV
SYNCHRONOUS
RECTIFIER
COMPARATOR
V
SR
Rgm
V
C
CURRENT
COMPARATOR
+
–
TRANSCONDUCTANCE
AMPLIFIER
–
+
1.25V
V
FB
+
–
–18mV
I
SENSE
I
L
R
SENSE
R1
R2
Figure 1. Buck Controller Functional Diagram
4
REV. 1.0 10/12/2000
ML4880
The oscillator/one shot block generates a constant ON-
time and a minimum OFF-time. The OFF-time is extended
for as long as the output of the current comparator stays
low. Note that the inductor current flows in the current
sense resistor during the OFF-time. Therefore, a minimum
OFF-time is required to allow for the finite circuit delays
in sensing the inductor current. The ON-time is triggered
when the current comparator’s output goes high. However,
unlike conventional fixed ON-time controllers, the
ML4880’s one shot has an inverse relationship with the
input voltage as shown in Figure 4. Figure 5 plots the
inductor voltage-ON-time product. Note that the volt-
second product is nearly constant at voltages above 7V
input. This results in an inductor current ripple of:
T
×
(V
IN
−
V
OUT
)
∆I
L
=
ON
L
which in turn raises the inductor current trip level,
shortening the OFF-time. At some level of increasing the
output load, the transconductance amplifier can no longer
continue to increase its output current. When this occurs,
the voltage across R
gm
reaches a maximum and the
inductor current cannot increase. If the inductor current
tries to increase, the voltage developed across the current
sense resistor would become more negative, causing the
non-inverting input of the current comparator to be
negative, which extends the OFF-time and reduces the
inductor current.
When the output voltage is too high, the
transconductance amplifier’s output current will
eventually become negative. However, since the inductor
current flows in only one direction (assuming no shoot
through current) the non-inverting input of the current
comparator will also stay negative. This extends the OFF-
time allowing the inductor current to decrease to zero and
causing the converter to stop operation until the output
voltage drops enough to increase the output current of the
transconductance amp above zero.
In summary, the three operation modes can be defined by
the voltage at the I
SENSE
pin at the end of the OFF-time:
V
SENSE
• 0V
0V > V
SENSE
> –140mV
Discontinuous
current mode
Continuous
current mode
(1)
It is important to note that the ripple current does not vary
in proportion with V
IN
, but remains nearly constant over a
wide input voltage range.
The transconductance amplifier generates a current from
the voltage difference between the reference and the
feedback voltage, V
FB
. This current produces a voltage
across Rgm that adds to the negative voltage that is
developed across the current sense resistor. When the
current level in the inductor drops low enough (a less
negative sense voltage) to cause the voltage at the non-
inverting input of the current comparator to go positive,
the comparator trips and starts a new ON cycle. In other
words, the current programming comparator controls the
length of the OFF-time by waiting until the inductor
current decreases to a value determined by the
transconductance amplifier.
This technique allows the feedback transconductance
amplifier’s output current to steer the current level in the
inductor. The higher the transconductance amplifier’s
output current, the higher the inductor current. For
example, when the output voltage drops due to a load
increase, the transconductance amplifier will increase its
output current and generate a larger voltage across R
gm
,
–140mV > V
SENSE
> –250mV Current limit
The synchronous rectifier comparator and the two NOR
gates make up the synchronous rectifier control circuit.
The synchronous control does not influence the operation
of the main control loop, and operation with a Schottky
diode in place of the synchronous rectifier is possible, but
at a lower conversion efficiency. The synchronous rectifier
(N DRV) is turned on during the minimum OFF-time or
whenever the I
SENSE
pin goes below –18mV. N DRV will
remain on until a new ON-time is started or until the
I
SENSE
pin goes above –18mV. When the ISENSE pin goes
above –18mV, the current in the inductor has gone to zero
V
C
T
ON
T
OFF(MIN)
V
SR
I
L
Figure 2. One Shot and Synchronous Rectifier Timing Diagram
REV. 1.0 10/12/2000
5
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