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LP2992
SNVS171J – NOVEMBER 2001 – REVISED JANUARY 2017
LP2992 Micropower 250-mA Low-Noise Ultra-Low-Dropout Regulator in SOT-23 and
WSON Packages Designed for Use With Very Low-ESR Output Capacitors
1 Features
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1
3 Description
The LP2992 is a 250-mA, fixed-output voltage
regulator designed to provide ultra-low dropout and
low noise in battery-powered applications.
Using an optimized vertically integrated PNP (VIP)
process, the LP2992 delivers unequaled performance
in all specifications critical to battery-powered
designs:
• Dropout voltage: Typically 450 mV at 250-mA
load, and 5 mV at 1-mA load.
• Ground pin current: Typically 1500 µA at 250-mA
load, and 75 µA at 1-mA load.
• Enhanced stability: The LP2992 is stable with
output capacitor equivalent series resistance
(ESR) as low as 5 mΩ, which allows the use of
ceramic capacitors on the output.
• Sleep mode: Less than 1-µA quiescent current
when ON/OFF pin is pulled low.
• Smallest possible size: SOT-23 and WSON
packages use absolute minimum board space.
• Precision output: 1% tolerance output voltages
available (A grade).
• Low noise: By adding a 10-nF bypass capacitor,
output noise can be reduced to 30 µV (typical).
• Multiple voltage options, from 1.5 V to 5 V, are
available as standard products. Consult factory for
custom voltages.
Device Information
(1)
PART NUMBER
LP2992
PACKAGE
WSON (6)
SOT-23 (5)
BODY SIZE (NOM)
3.29 mm × 2.92 mm
2.90 mm × 1.60 mm
•
•
Input Voltage Range: 2.2 V to 16 V
Output Voltage Range: 1.5 V to 5 V
Wide Supply Voltage Range (16-V Maximum)
Output Voltage Accuracy 1% (A Grade)
Ultra-Low-Dropout Voltage
Specified 250-mA Output Current
Stable With Low-ESR Output Capacitor
< 1-µA Quiescent Current When Shut Down
Low Ground Pin Current at All Loads
High Peak Current Capability
Low Z
OUT
: 0.3-Ω Typical (10 Hz to 1 MHz)
Overtemperature and Overcurrent Protection
−40°C
to +125°C Junction Temperature Range
Smallest Possible Size (SOT-23, WSON
Package)
Requires Minimum External Components
Custom Voltages Available
2 Applications
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Cellular Phones
Palmtop/Laptop Computers
Personal Digital Assistants (PDA)
Camcorders, Personal Stereos, Cameras
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
V
IN
IN
C
IN
OUT
C
OUT
V
OUT
LP2992
GND
V
ON/OFF
ON/OFF
ON
OFF
BYPASS
C
BYPASS
Copyright © 2017, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LP2992
SNVS171J – NOVEMBER 2001 – REVISED JANUARY 2017
www.ti.com
Table of Contents
1
2
3
4
5
6
Features
..................................................................
Applications
...........................................................
Description
.............................................................
Revision History.....................................................
Pin Configuration and Functions
.........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Typical Characteristics ..............................................
Overview .................................................................
Functional Block Diagram .......................................
Feature Description.................................................
Device Functional Modes........................................
1
1
1
2
3
4
4
4
4
5
5
7
8
Application and Implementation
........................
15
8.1 Application Information............................................
15
8.2 Typical Application .................................................
15
9 Power Supply Recommendations......................
20
10 Layout...................................................................
21
10.1 Layout Guidelines .................................................
21
10.2 Layout Examples...................................................
21
10.3 WSON Mounting ...................................................
21
11 Device and Documentation Support
.................
22
11.1
11.2
11.3
11.4
11.5
11.6
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
22
22
22
22
22
22
7
Detailed Description
............................................
13
7.1
7.2
7.3
7.4
13
13
13
14
12 Mechanical, Packaging, and Orderable
Information
...........................................................
22
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision I (November 2015) to Revision J
•
•
Page
Deleted specific values from capacitors in
Simplified Schematic
drawing ............................................................................
1
Added
Receiving Notification of Documentation Updates
...................................................................................................
22
Changes from Revision H (January 2015) to Revision I
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•
•
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Page
Added top navigator icon for TI Design .................................................................................................................................
1
Changed "174.2°C/W" to "169.7°C/W" in footnote 3 to
Abs Max
table. ................................................................................
4
Changed
ESD Ratings
table to differentiate different values for different pins/packages. ....................................................
4
Added new footnotes 2 and 3 to
Thermal Information
table; update thermal values for DBV (SOT-23) package. ...............
5
Added
Power Dissipation
and
Estimating Junction Temperature
subsections ...................................................................
18
Added additional related document links .............................................................................................................................
22
Changes from Revision G (March 2013) to Revision H
•
Page
Added
Device Information
and
ESD Ratings
tables,
Pin Configuration and Functions, Feature Description
,
Device
Functional Modes, Application and Implementation, Power Supply Recommendations, Layout
,
Device and
Documentation Support
, and
Mechanical, Packaging, and Orderable Information
sections; update
Thermal Values
and pin names ........................................................................................................................................................................
1
Changes from Revision F (March 2013) to Revision G
•
Page
Changed Changed layout of National Semiconductor data sheet to TI format .....................................................................
1
2
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LP2992
Copyright © 2001–2017, Texas Instruments Incorporated
LP2992
www.ti.com
SNVS171J – NOVEMBER 2001 – REVISED JANUARY 2017
5 Pin Configuration and Functions
DBV Package
5-Pin SOT-23
Top View
NGD Package
6-Pin WSON
Top View
Pin Functions
PIN
NAME
BYPASS
GND
IN
–
ON/OFF
OUT
DBV
4
2
1
–
3
5
NAME
BYPASS
GND
IN
N/C
ON/OFF
OUT
NGD
1
2
4
5
3
6
I/O
I
–
I
–
I
O
DESCRIPTION
Bypass capacitor for low-noise operation.
Ground.
Unregulated input voltage.
No internal connection. Connect to GND or leave open.
A low voltage on this pin disables the device, and the regulator enters
a sleep mode. A high voltage on this pin enables the device.
Regulated output voltage. This pin requires an output capacitor to
maintain stability. See the
Detailed Design Procedure
for output
capacitor details.
The exposed die attach pad on the bottom of the package must be
connected to a copper thermal pad on the PCB at ground potential.
Connect to ground potential or leave floating. Do not connect to any
potential other than the same ground potential seen at device pin 2.
—
—
DAP
Exposed
thermal pad
—
Copyright © 2001–2017, Texas Instruments Incorporated
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3
LP2992
SNVS171J – NOVEMBER 2001 – REVISED JANUARY 2017
www.ti.com
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1) (2)
MIN
Lead temperature (soldering, 5 seconds)
Power dissipation
(3)
MAX
260
UNIT
°C
V
V
V
V
°C
Internally Limited
−0.3
−0.3
−0.3
(5)
Input supply voltage (survival)
Shutdown input voltage (survival)
Output voltage (survival)
I
OUT
(survival)
Input-output voltage (survival)
Storage temperature, T
stg
(1)
(2)
(3)
(4)
16
16
9
16
150
Short-circuit protected
−0.3
−65
(4)
(5)
Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended
Operating Conditions.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
If Military- or Aerospace-specified devices are required, contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
The maximum allowable power dissipation is a function of the maximum junction temperature, T
J(MAX)
, the junction-to-ambient thermal
resistance, R
θJA
, and the ambient temperature, T
A
. The maximum allowable power dissipation at any ambient temperature is calculated
using:
P
(MAX)
= (T
J(MAX)
– T
A
) / R
θJA
Where the value of R
θJA
for the SOT-23 package is 169.7°C/W in a typical PC board mounting and the WSON package is 72.3°C/W.
Exceeding the maximum allowable dissipation causes excessive die temperature, and the regulator goes into thermal shutdown.
If used in a dual-supply system where the regulator load is returned to a negative supply, the LP2992 output must be diode-clamped to
ground.
The output PNP structure contains a diode between the IN to OUT pins that is normally reverse-biased. Reversing the polarity from V
IN
to V
OUT
turns on this diode.
6.2 ESD Ratings
VALUE
Electrostatic
discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001
(1)
Pins 3 and 4 (SOT)
Pins 1 and 3 (WSON)
All pins except 3 and 4 (SOT)
All pins except 1 and 3 (WSON)
±1000
V
±2000
UNIT
V
(ESD)
(1)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
V
IN
V
ON/OFF
I
OUT
T
J
(1)
Input supply voltage
ON/OFF input voltage
Output current
Operating junction temperature
–40
2.2
(1)
MAX
16
V
IN
250
125
UNIT
V
V
mA
°C
0
Recommended minimum V
IN
is the greater of 2.2 V or V
OUT
+ rated dropout voltage (maximum) for operating load current.
4
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Copyright © 2001–2017, Texas Instruments Incorporated
LP2992
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SNVS171J – NOVEMBER 2001 – REVISED JANUARY 2017
6.4 Thermal Information
LP2992
THERMAL METRIC
R
θJA
(3)
R
θJC(top)
R
θJB
ψ
JT
ψ
JB
R
θJC(bot)
(1)
(2)
(3)
(1)
DBV (SOT-23)
5 PINS
169.7
122.6
29.9
16.7
29.4
n/a
NGD (WSON)
(2)
6 PINS
72.3
81.6
39.5
2.0
39.2
11.6
UNIT
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance, High K
Junction-to-board thermal resistance
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
For more information about traditional and new thermal metrics, see the
Semiconductor and IC Package Thermal Metrics.
The PCB for the NGD (WSON) package R
θJA
includes two (2) thermal vias under the exposed thermal pad per EIA/JEDEC JESD51-5.
Thermal resistance value R
θJA
is based on the EIA/JEDEC High-K printed circuit board defined by: JESD51-7 - High Effective Thermal
Conductivity Test Board for Leaded Surface Mount Packages.
6.5 Electrical Characteristics
Unless otherwise specified: V
IN
= V
OUT(NOM)
+ 1 V, I
L
= 1 mA, C
IN
= 1 µF, C
OUT
= 4.7 µF, V
ON/OFF
= 2 V. MIN (minimum) and
MAX (maximum) limits apply over the recommended operating temperature range unless otherwise noted; typical limits apply
for T
A
= T
J
= 25°C.
PARAMETER
TEST CONDITIONS
I
L
= 1 mA, T
J
= 25°C
1 mA
≤
I
L
≤
50 mA, T
J
= 25°C
ΔV
OUT
Output voltage tolerance
1 mA
≤
I
L
≤
50 mA
1 mA
≤
I
L
≤
250 mA, T
J
= 25°C
1 mA
≤
I
L
≤
250 mA
ΔV
OUT
/ΔV
IN
V
IN
(min)
Output voltage line regulation
V
OUT(NOM)
+ 1 V
≤
V
IN
≤
16 V
T
J
= 25°C
V
OUT(NOM)
+ 1 V
≤
V
IN
≤
16 V
Minimum input voltage required to maintain output regulation
I
L
= 0 mA, T
J
= 25°C
I
L
= 0 mA
I
L
= 1 mA, T
J
= 25°C
I
L
= 1 mA
V
IN
– V
OUT
Dropout voltage
(2)
I
L
= 50 mA, T
J
= 25°C
I
L
= 50 mA
I
L
= 150 mA, T
J
= 25°C
I
L
= 150 mA
I
L
= 250 mA, T
J
= 25°C
I
L
= 250 mA
450
260
100
5
2.05
0.5
0.007
TYP
LP2992AI-X.X
(1)
MIN
−1
−1.5
−2.5
−3.5
−4.5
MAX
1
1.5
2.5
3.5
4.5
0.014
0.032
2.2
2.5
4
9
12
125
180
325
470
575
850
LP2992I-X.X
(1)
MIN
−1.5
−2.5
−3.5
−4
−5
MAX
1.5
2.5
3.5 %V
NOM
4
5
0.014
0.032
2.2
2.5
4
9
12
125
180
325
470
575
850
mV
V
%/V
UNIT
(1)
(2)
Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using
Statistical Quality Control (SQC) methods. The limits are used to calculate TI's Average Outgoing Quality Level (AOQL).
V
IN
must be the greater of 2.2 V or V
OUT(NOM)
+ dropout voltage to maintain output regulation. Dropout voltage is defined as the input-to-
output differential at which the output voltage drops 2% below the value measured with a 1-V differential.
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