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LMH1219
SNLS530D – APRIL 2016 – REVISED JUNE 2018
LMH1219 Low Power 12G UHD Adaptive Cable Equalizer with Integrated Reclocker
1 Features
1
3 Description
The LMH1219 is a low-power, dual-input and dual-
output, adaptive equalizer with integrated reclocker. It
supports SMPTE video rates up to 11.88 Gbps and
10 GbE video over IP, enabling UHD video for 4K/8K
applications. An extended reach adaptive cable
equalizer at IN0 is designed to equalize data
transmitted over 75
Ω
coaxial cable and operates
over a wide range of data rates from 125 Mbps to
11.88 Gbps. An adaptive board trace equalizer at IN1
is SFF-8431 compatible and supports both SMPTE
and 10 GbE data rates.
The integrated reclocker attenuates high frequency
jitter and provides the best signal integrity. High input
jitter tolerance of the reclocker improves timing
margin. The reclocker has a built-in loop filter, and
operates without the need of a precision input
reference clock. A non-disruptive eye monitor allows
real time measurement of the serial data to simplify
system debug and accelerate board bring-up.
The integrated 2:1 Mux and 1:2 Fanout provide
flexibility for multiple video signals. The output drivers
offer programmable de-emphasis to compensate
board trace losses at its outputs. The integrated
return loss network meets stringent SMPTE
specifications across all data rates. The typical power
consumption of LMH1219 is 250 mW. In the absence
of input signal, power is further reduced to 16 mW.
The LMH1219 is pin compatible to LMH1226 (12G
UHD reclocker) and LMH0324 (3G adaptive cable
equalizer).
Device Information
(1)
PART NUMBER
LMH1219
PACKAGE
QFN (24)
BODY SIZE (NOM)
4.00 mm × 4.00 mm
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Supports ST-2082-1(12G), ST-2081-1(6G), ST-
424(3G), ST-292(HD), and ST-259(SD)
Supports SFF8431 (SFP+) for SMPTE 2022-5/6
Compatible with DVB-ASI and AES10 (MADI)
Integrated Reference-Less Reclocker Locks to
SMPTE and 10GbE Rate: 11.88 Gbps, 5.94 Gbps,
2.97 Gbps, 1.485 Gbps, or Divide-by-1.001 Sub-
Rates, 270 Mbps and 10.3125 Gbps
Adaptive Cable Equalizer at Input 0 (IN0)
Cable Reach (Belden 1694A):
– 75 m at 11.88 Gbps (4Kp60 UHD)
– 120 m at 5.94 Gbps (UHD)
– 200 m at 2.97 Gbps (FHD)
– 280 m at 1.485 Gbps (HD)
– 600 m at 270 Mbps (SD)
Adaptive Board Trace Equalizer at Input 1 (IN1)
Low Power: 250 mW (Typical)
Power Saving Mode: 16 mW
Integrated Input Return Loss Network
2:1 Input Mux, 1:2 Fanout Output With De-
Emphasis
Supports Signal Splitter Mode (–6 dB Launch
Amplitude)
On-Chip Loop Filter Capacitor and Eye Monitor
Powers from Single 2.5 V with On-Chip 1.8 V
Regulator
Configurable by Control Pins, SPI, or SMBus
Interface
4 mm × 4 mm 24-pin QFN Package
Operating Temperature Range: –40°C to +85°C
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
•
•
•
SMPTE Compatible Serial Digital Interface
UHDTV/4K/8K/HDTV/SDTV Video
Broadcast Video Routers, Switchers, Distribution
Amplifiers, and Monitors
Digital Video Processing and Editing
10 GbE - SDI Media Gateway
2 SE 75
Ÿ
Term
Simplified Block Diagram
IN0±
Cable
EQ
100-Ÿ
Driver
2
OUT0±
IN1±
2 Diff 100
Ÿ
Term
PCB
EQ
Reclocker
Data
with
Integrated
Clock
LoopFilter,
EyeMon
IN_MUX
OUT_MUX
100-Ÿ
Driver
2
OUT1±
LDO
Power
Management
Control Logic
Serial
Interface
VDD_LDO
Single 2.5 V
or
Dual 2.5 V and 1.8 V
Control
Lock
Pins Indicator
SPI
or
SMBus
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMH1219
SNLS530D – APRIL 2016 – REVISED JUNE 2018
www.ti.com
Table of Contents
1
2
3
4
5
6
Features
..................................................................
Applications
...........................................................
Description
.............................................................
Revision History.....................................................
Pin Configuration and Functions
.........................
Specifications.........................................................
6.1
6.2
6.3
6.4
6.5
6.6
1
1
1
2
3
5
7.3 Feature Description.................................................
17
7.4 Device Functional Modes........................................
22
7.5 LMH1219 Register Map ..........................................
27
8
Application and Implementation
........................
40
8.1 Application Information............................................
40
8.2 Typical Application ..................................................
40
Absolute Maximum Ratings ......................................
5
ESD Ratings ............................................................
5
Recommended Operating Conditions.......................
5
Thermal Information ..................................................
6
Electrical Characteristics...........................................
6
Recommended SMBus Interface AC Timing
Specifications ...........................................................
12
6.7 Serial Parallel Interface (SPI) AC Timing
Specifications ...........................................................
13
6.8 Typical Characteristics ............................................
14
9 Power Supply Recommendations......................
47
10 Layout...................................................................
47
10.1 PCB Layout Guidelines.........................................
47
10.2 Layout Example ....................................................
49
11 Device and Documentation Support
.................
50
11.1
11.2
11.3
11.4
11.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
50
50
50
50
50
7
Detailed Description
............................................
16
7.1 Overview .................................................................
16
7.2 Functional Block Diagram .......................................
16
12 Mechanical, Packaging, and Orderable
Information
...........................................................
50
4 Revision History
Changes from Revision C (October 2017) to Revision D
•
•
Page
First public release of full production data sheet; add top navigator link for TI reference design..........................................
1
Moved
LMH1219 and LMH0324 Compatibility
to
Application Information
...........................................................................
40
Changes from Revision B (February 2017) to Revision C
•
Page
add package drawings..........................................................................................................................................................
50
Changes from Revision A (May 2016) to Revision B
•
•
Page
Changed eq_en_bypass bit description from "Gain Stages 3 and 4" to "Gain Stages 2 and 3" ........................................
29
Changed bit location of IN1 Carrier Detect Power Down Control from Reg 0x13[5] to Reg 0x15[6] ..................................
29
Changes from Original (April 2016) to Revision A
•
•
•
•
Page
Deleted min and max VOD_DE amplitude specification when VOD_DE = Level F .............................................................
9
Changed typical VOD_DE amplitude specifications for Levels F, R, and L ..........................................................................
9
Changed DEM value and DEM register settings in
Table 5
to match correct VOD_DE pin logic levels .............................
20
Added new row for VOD = 5, DEM = 5 setting in
Table 10
................................................................................................
43
2
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LMH1219
Copyright © 2016–2018, Texas Instruments Incorporated
LMH1219
www.ti.com
SNLS530D – APRIL 2016 – REVISED JUNE 2018
5 Pin Configuration and Functions
RTW Package
24-Pin QFN
Top View
MISO_ADDR1
20
OUT_CTRL
19
18
17
VDD_LDO
SCK_SCL
21
24
23
IN0+
IN0-
VSS
IN1+
IN1-
MODE_SEL
1
2
3
4
5
6
EP = VSS
22
VDDIO
VIN
OUT0+
OUT0-
VSS
OUT1+
OUT1-
VDD_CDR
LMH1219
16
15
14
13
10
11
VOD_DE
SS_N_ADDR0
IN_OUT_SEL
MOSI_SDA
VSS
Pin Functions
PIN
NAME
IN0+
IN0-
IN1+
IN1-
OUT0+
OUT0-
OUT1+
OUT1-
Control Pins
LOCK_N is the reclocker lock indicator for the selected input. LOCK_N is pulled LOW
when the reclocker has acquired locking condition. LOCK_N is an open drain output,
3.3 V tolerant, and requires an external 2-kΩ to 5-kΩ pull-up resistor to logic supply.
LOCK_N pin can be re-configured to indicate CD_N (Carrier Detect) or INT_N
(Interrupt) for IN0 or IN1 through register programming.
IN_OUT_SEL selects the signal flow at input ports to output ports. See
Table 2
for
details. This pin setting can be overridden by register control.
OUT_CTRL selects the signal flow from the selected IN port to OUT0± and OUT1±. It
selects reclocked data, reclocked data and clock, bypassed reclocker data (equalized
data to output driver), or bypassed equalizer and reclocker data. See
Table 4
for
details. This pin setting can be overridden by register control.
NO.
1
2
4
5
18
17
15
14
High Speed Differential I/O'S
I, Analog
I, Analog
I, Analog
I, Analog
O, Analog
O, Analog
O, Analog
O, Analog
Single-ended complementary inputs, 75-Ω internal termination from IN0+ or IN0- to
internal common mode voltage and return loss compensation network. Requires
external 4.7-µF AC coupling capacitors. IN0+ is the 75-Ω input port for the adaptive
cable equalizer in SMPTE video applications.
Differential complementary inputs with internal 100-Ω termination. Requires external
4.7-µF AC coupling capacitors for SMPTE and 10 GbE.
Differential complementary outputs with 100-Ω internal termination. Requires external
4.7-µF AC coupling capacitors. Output driver OUT0± can be disabled under user
control.
Differential complementary outputs with 100-Ω internal termination. Requires external
4.7-µF AC coupling capacitors. Output driver OUT1± can be disabled under user
control.
I/O
(1)
DESCRIPTION
LOCK_N
12
O, LVCMOS, OD
IN_OUT_SEL
8
I, 4-LEVEL
OUT_CTRL
19
I, 4-LEVEL
(1)
I = Input, O = Output, IO = Input or Output, OD = Open Drain, LVCMOS = 2-State Logic, 4-LEVEL = 4-State Logic
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Copyright © 2016–2018, Texas Instruments Incorporated
LOCK_N
12
7
8
9
LMH1219
SNLS530D – APRIL 2016 – REVISED JUNE 2018
www.ti.com
Pin Functions (continued)
PIN
NAME
VOD_DE
MODE_SEL
NO.
11
6
I/O
(1)
DESCRIPTION
VOD_DE selects the driver output amplitude and de-emphasis level for both OUT0±
and OUT1±. See
Table 5
for details. This pin setting can be overridden by register
control.
MODE_SEL enables SPI or SMBus serial control interface. See
Table 6
for details.
SS_N is the Slave Select. When SS_N is at logic Low, it enables SPI access to the
LMH1219 slave device. SS_N is a LVCMOS input referenced to VDDIO.
MISO is the SPI control serial data output from the LMH1219 slave device. MISO is a
LVCMOS output referenced to VDDIO.
MOSI is used as the SPI control serial data input to the LMH1219 slave device. MOSI
is LVCMOS input referenced to VDDIO.
SCK is the SPI serial input clock to the LMH1219 slave device. SCK is LVCMOS
referenced to VDDIO.
I, 4-LEVEL
I, 4-LEVEL
Serial Control Interface (SPI Mode), MODE_SEL = F (Float)
SS_N
MISO
MOSI
SCK
7
20
10
21
I, LVCMOS
O, LVCMOS
I, LVCMOS
I, LVCMOS
Serial Control Interface (SMBus MODE) , MODE_SEL = L (1 kΩ to VSS)
ADDR0
ADDR1
SDA
7
20
10
Strap, 4-LEVEL
Strap, 4-LEVEL
IO, LVCMOS, OD
ADDR[1:0] are SMBus address straps to select one of the 16 supported SMBus
addresses. ADDR[1:0] are 4-level straps and are read into the device at power up.
SDA is the SMBus bi-directional open drain SDA data line to or from the LMH1219
slave device. SDA is an open drain IO and tolerant to 3.3 V. SDA requires an external
2-kΩ to 5-kΩ pull-up resistor to the SMBus termination voltage.
SCL is the SMBus input clock to the LMH1219 slave device. It is driven by a
LVCMOS open drain driver from the SMBus master. SCL is tolerant to 3.3 V and
requires an external 2-kΩ to 5-kΩ pull up resistor to the SMBus termination voltage.
Ground reference.
VIN is connected to an external power supply. It accepts either 2.5 V ± 5% or 1.8 V ±
5%. When VIN is powered from 2.5 V, VDD_LDO is the output of an on-chip LDO
regulator. For lower power operation, both VIN and VDD_LDO should be connected
to a 1.8 V supply.
VDDIO powers the LVCMOS IO and 4-level input logic and connects to 2.5 V ± 5%.
VDD_LDO is the output of the internal 1.8 V LDO regulator when VIN is connected to
a 2.5 V supply. VDD_LDO output requires external 1-µF and 0.1-µF bypass
capacitors to VSS. The internal LDO is designed to power internal circuitry only.
VDD_LDO is an input when VIN is powered from 1.8 V for lower power operation.
When VIN is connected to a 1.8 V supply, both VIN and VDD_LDO should be
connected to a 1.8 V supply.
VDD_CDR powers the reclocker circuitry and connects to 2.5 V ± 5% supply.
EP is the exposed pad at the bottom of the QFN package. The exposed pad must be
connected to the ground plane through a via array. See
Figure 41
for details.
SCL
Power
VSS
VIN
VDDIO
21
I, LVCMOS, OD
3, 9, 16
24
22
I, Ground
I, Power
I, Power
VDD_LDO
23
IO, Power
VDD_CDR
EP
13
I, Power
I, Ground
4
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SNLS530D – APRIL 2016 – REVISED JUNE 2018
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
Supply Voltage for 2.5 V Mode (VDD_CDR, VIN, VDDIO)
Supply Voltage for 1.8 V Mode (VIN, VDD_LDO)
4-Level Input/Output Voltage (IN_OUT_SEL, OUT_CTRL, VOD_DE, MODE_SEL, ADDR0,
ADDR1)
SMBus Input/Output Voltage (SDA, SCL)
SPI Input/Output Voltage (SS_N, MISO, MOSI, and SCK)
Input Voltage (IN0±, IN1±)
Input Current (IN0±, IN1±)
Junction Temperature
Storage temperature
(1)
(2)
-65
(1) (2)
MIN
–0.5
–0.5
–0.5
–0.5
–0.5
–0.5
–30
MAX
2.75
2.0
2.75
4.0
2.75
2.75
30
125
150
UNIT
V
V
V
V
V
V
mA
°C
°C
Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended
Operating Conditions.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
For soldering specifications, see application note
SNOA549.
6.2 ESD Ratings
VALUE
V
(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
(1)
Charged-device model (CDM), per JEDEC specification JESD22-C101
(2)
UNIT
V
±4500
±1500
JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500 V HBM is possible with the necessary precautions. Pins listed as ±4500 V may actually have higher performance.
JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250 V CDM is possible with the necessary precautions. Pins listed as ±1500 V may actually have higher performance.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
Single Supply
Mode
(1)
Dual Supply
Mode
(2) (3)
VDD
SMBUS
V
IN0_LAUNCH
V
IN1_LAUNCH
T
JUNCTION
T
AMBIENT
NTps
max
(1)
(2)
(3)
(4)
(4)
NOM
2.5
1.8
2.5
0.8
0.4
MAX
2.625
1.89
2.625
3.6
0.88
0.44
850
1000
100
UNIT
V
V
V
Vp-p
mVp-p
°C
°C
mVp-p
VIN, VDDIO, VDD_CDR to VSS
VIN, VDD_LDO to VSS
VDD_CDR, VDDIO to VSS
SMBus: SDA, SCL Open Drain Termination Voltage
Source Launch Amplitude before coaxial
cable
Source Differential Launch Amplitude
Operating Junction Temperature
Ambient Temperature
50 Hz to 1 MHz, sinusoidal
Maximum Supply Noise Tolerance
1.1 MHz to 6 GHz,
sinusoidal
Normal mode
Splitter mode
before 5-inch board trace
before 20-inch board trace
2.375
1.71
2.375
2.375
0.72
0.36
300
650
–40
25
<20
<10
85
In Single Supply Mode, the VIN, VDDIO and VDD_CDR supplies are 2.5 V. The VDD_LDO is the 1.8 V LDO output of an internal LDO
regulator, the VDD_LDO pin should not be connected to any external supply voltage.
In Dual Supply Mode, the VIN and VDD_LDO are connected to a 1.8 V supply, while the VDD_CDR and VDDIO supplies are 2.5 V.
In Dual Supply Mode, the VDDIO and VDD_CDR supply should be powered before or at the same time as VIN and VDD_LDO = 1.8 V.
The sum of the DC supply voltage and AC supply noise should not exceed the recommended supply voltage range.
Copyright © 2016–2018, Texas Instruments Incorporated
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