EH3625ETTS-7.3728M TR
EH36 25 ET
Series
RoHS Compliant (Pb-free) 3.3V 4 Pad 3.2mm x 5mm
Ceramic SMD LVCMOS High Frequency Oscillator
Frequency Tolerance/Stability
±25ppm Maximum
Operating Temperature Range
-40°C to +85°C
Duty Cycle
50 ±10(%)
RoHS
Pb
Packaging Options
Tape & Reel
TS -7.3728M TR
Nominal Frequency
7.3728MHz
Pin 1 Connection
Tri-State (High Impedance)
ELECTRICAL SPECIFICATIONS
Nominal Frequency
Frequency Tolerance/Stability
7.3728MHz
±25ppm Maximum (Inclusive of all conditions: Calibration Tolerance at 25°C, Frequency Stability over the
Operating Temperature Range, Supply Voltage Change, Output Load Change, 1st Year Aging at 25°C,
Shock, and Vibration)
±5ppm/year Maximum
-40°C to +85°C
3.3Vdc ±0.3Vdc
35mA Maximum (No Load)
2.7Vdc Minimum (IOH = -8mA)
0.5Vdc Maximum (IOL = +8mA)
6nSec Maximum (Measured at 20% to 80% of waveform)
50 ±10(%) (Measured at 50% of waveform)
30pF Maximum
CMOS
Tri-State (High Impedance)
70% of Vdd Minimum to enable output, 20% of Vdd Maximum to disable output, No Connect to enable
output.
±250pSec Maximum, ±100pSec Typical
±50pSec Maximum, ±40pSec Typical
10mSec Maximum
-55°C to +125°C
Aging at 25°C
Operating Temperature Range
Supply Voltage
Input Current
Output Voltage Logic High (Voh)
Output Voltage Logic Low (Vol)
Rise/Fall Time
Duty Cycle
Load Drive Capability
Output Logic Type
Pin 1 Connection
Tri-State Input Voltage (Vih and Vil)
Absolute Clock Jitter
One Sigma Clock Period Jitter
Start Up Time
Storage Temperature Range
ENVIRONMENTAL & MECHANICAL SPECIFICATIONS
Fine Leak Test
Gross Leak Test
Mechanical Shock
Resistance to Soldering Heat
Resistance to Solvents
Solderability
Temperature Cycling
Vibration
MIL-STD-883, Method 1014, Condition A
MIL-STD-883, Method 1014, Condition C
MIL-STD-202, Method 213, Condition C
MIL-STD-202, Method 210
MIL-STD-202, Method 215
MIL-STD-883, Method 2003
MIL-STD-883, MEthod 1010
MIL-STD-883, Method 2007, Condition A
www.ecliptek.com | Specification Subject to Change Without Notice | Rev C 8/13/2010 | Page 1 of 6
EH3625ETTS-7.3728M TR
MECHANICAL DIMENSIONS (all dimensions in millimeters)
PIN
1
2
3
4
CONNECTION
Tri-State
Ground/Case Ground
Output
Supply Voltage
3.20
±0.20
MARKING
ORIENTATION
1.14
1.0
All Tolerances are ±0.1
1.20 ±0.20 (x4)
1.00 ±0.20 (x4)
4
5.00
±0.20
2.54
±0.15
3
1.3
MAX
2.20
±0.15
2
1
1.20
±0.20
(x4)
LINE MARKING
1
E7.3728
E=Ecliptek Designator
Suggested Solder Pad Layout
All Dimensions in Millimeters
1.2 (X4)
1.4 (X4)
Solder Land
(X4)
www.ecliptek.com | Specification Subject to Change Without Notice | Rev C 8/13/2010 | Page 2 of 6
EH3625ETTS-7.3728M TR
OUTPUT WAVEFORM & TIMING DIAGRAM
TRI-STATE INPUT
V
IH
V
IL
CLOCK OUTPUT
V
OH
80% of Waveform
50% of Waveform
20% of Waveform
V
OL
OUTPUT DISABLE
(HIGH IMPEDANCE
STATE)
t
PLZ
Fall
Time
Rise
Time
T
W
T
Duty Cycle (%) = T
W
/T x 100
t
PZL
Test Circuit for CMOS Output
Oscilloscope
Frequency
Counter
+
+
Power
Supply
_
+
Voltage
Meter
_
Current
Meter
_
Supply
Voltage
(V
DD
)
Probe
(Note 2)
Output
0.01µF
(Note 1)
0.1µF
(Note 1)
Ground
C
L
(Note 3)
No Connect
or Tri-State
Note 1: An external 0.1µF low frequency tantalum bypass capacitor in parallel with a 0.01µF high frequency
ceramic bypass capacitor close to the package ground and V
DD
pin is required.
Note 2: A low capacitance (<12pF), 10X attenuation factor, high impedance (>10Mohms), and high bandwidth
(>300MHz) passive probe is recommended.
Note 3: Capacitance value C
L
includes sum of all probe and fixture capacitance.
www.ecliptek.com | Specification Subject to Change Without Notice | Rev C 8/13/2010 | Page 3 of 6
EH3625ETTS-7.3728M TR
Tape & Reel Dimensions
Quantity Per Reel: 1,000 units
4.0 ±0.1
2.0 ±0.1
DIA 1.5 +0.1/-0.0
0.30 ±0.05
5.5 ±0.1
12.0 ±0.2
6.5 ±0.1
A0*
8.0 ±0.1
*Compliant to EIA 481A
B0*
K0*
1.5 MIN
DIA 40 MIN
Access Hole at
Slot Location
18.4 MAX
180 MAX
DIA 50 MIN
DIA 20.2 MIN
2.5 MIN Width
10.0 MIN Depth
Tape slot in Core
for Tape Start
12.4 +2.0/-0.0
DIA 13.0 ±0.2
www.ecliptek.com | Specification Subject to Change Without Notice | Rev C 8/13/2010 | Page 4 of 6
EH3625ETTS-7.3728M TR
Recommended Solder Reflow Methods
T
P
Critical Zone
T
L
to T
P
Ramp-up
Ramp-down
Temperature (T)
T
L
T
S
Max
T
S
Min
t
S
Preheat
t 25°C to Peak
t
L
t
P
Time (t)
High Temperature Infrared/Convection
T
S
MAX to T
L
(Ramp-up Rate)
Preheat
- Temperature Minimum (T
S
MIN)
- Temperature Typical (T
S
TYP)
- Temperature Maximum (T
S
MAX)
- Time (t
S
MIN)
Ramp-up Rate (T
L
to T
P
)
Time Maintained Above:
- Temperature (T
L
)
- Time (t
L
)
Peak Temperature (T
P
)
Target Peak Temperature (T
P
Target)
Time within 5°C of actual peak (t
p
)
Ramp-down Rate
Time 25°C to Peak Temperature (t)
Moisture Sensitivity Level
3°C/second Maximum
150°C
175°C
200°C
60 - 180 Seconds
3°C/second Maximum
217°C
60 - 150 Seconds
260°C Maximum for 10 Seconds Maximum
250°C +0/-5°C
20 - 40 seconds
6°C/second Maximum
8 minutes Maximum
Level 1
www.ecliptek.com | Specification Subject to Change Without Notice | Rev C 8/13/2010 | Page 5 of 6
FPGA/CPLD
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