DSC512-05
Crystal-less™ Four Output Clock Generator
General Description
The DSC512-05 is a Crystal-less™, four
output clock generator that implements
Discera’s
proven
PureSilicon™
MEMS
technology. The device provides excellent
jitter and stability over a wide range of
supply voltages and temperatures.
By
eliminating the external quartz crystal,
MEMS
clock
generators
significantly
enhance reliability and accelerate product
development, while meeting stringent clock
performance criteria for a variety of
communications, storage, and networking
applications.
DSC512-05 has an Output Enable / Disable
feature allowing it to disable all outputs
when OE1 and OE2 are low. Each output
enable pin controls one of the two banks of
synchronous clocks. See the OE function
table 1 for more detail.
The device is
available in a 20 pin QFN. Additional output
formats are in any combination of LVPECL,
LVDS, LVCMOS and HCSL.
Features
Two 50MHz (LVDS) Clocks
One 14MHz (LVCMOS) Clock
One 16MHz (LVCMOS) Clock
Available Format on Any Output:
o
o
o
o
HCSL, LVPECL, LVDS or LVCMOS
Ext. Industrial: -40° to 105° C
Industrial: -40° to 85° C
Ext. commercial: -20° to 70° C
Wide Temperature Range
Supply Range of 2.25 to 3.6 V
Low Power Consumption
o
o
o
30% lower than competing devices
Qualified to MIL-STD-883
20 QFN
Excellent Shock & Vibration Immunity
Available Footprints:
Lead Free & RoHS Compliant
Block Diagram*
Short Lead Time: 2 Weeks
AEC-Q100 Automotive Qualified
Applications
Communications/Networking
Embedded and Industrial
Consumer and computation
Medical, Military, Avionics
Storage and enterprise
*
In the above block diagram:
Clk0+ is 14MHz LVCMOS (Clk0- is off)
Clk1+/- and Clk2 +/- are 50MHz LVDS;
Clk3 + is 16MHz LVCMOS (Clk3- is off)
For other frequencies, please contact the factor:
Sales@discera.com
_____________________________________________________________________________________________________________________________ _________________
DSC512-05
Page 1
DSC512-05
Crystal-less™ Four Output Clock Generator
Specifications
(Unless specified otherwise: T=25° C,
VDD =3.3V)
Parameter
Supply Voltage
1
Supply Current
Supply Current
2
(Four HCSL Outputs)
Frequency Stability
Startup Time
3
Input Logic Levels
Input logic high
Input logic low
Output Disable Time
4
Output Enable Time
Pull-Up Resistor
2
V
DD
I
DD
I
DD
Δf
t
SU
V
IH
V
IL
t
DA
t
EN
Pull-up on OE pin
40
EN pin low – outputs are
disabled
All outputs running, R
L
=50 Ω,
Includes frequency variations
due to initial tolerance, temp.
and power supply voltage
T=25°C
0.75xV
DD
-
Condition
Min.
2.25
Typ.
42
120
Max.
3.6
46
Unit
V
mA
mA
±100
±50
5
-
0.25xV
DD
5
20
ppm
ms
V
ns
ns
kΩ
LVDS Outputs
Supply Current
2
(All LVDS outputs)
Output offset Voltage
Delta Offset Voltage
Pk to Pk Output Swing
Output Transition time
3
Rise Time
Fall Time
Frequency
Output Duty Cycle
Period Jitter
Integrated Phase Noise
I
DD
V
OS
∆V
OS
All outputs running at 156.25MHz,
R
L
=100Ω
All outputs disabled
R
L
=100Ω Differential
Single-Ended
20% to 80%
R
L
=100Ω, C
L
= 2pF
At any output
Differential
200kHz to 20MHz @156.25MHz
100kHz to 20MHz @156.25MHz
12kHz to 20MHz @156.25MHz
2.3
48
1.125
110
29
TBD
TBD
1.4
50
mA
V
mV
mV
V
PP
t
R
t
F
f
0
SYM
J
PER
J
PH
350
200
TBD
460
52
2.5
0.28
0.4
1.7
ps
MHz
%
ps
RMS
ps
RMS
2
Notes:
1. Each V
DD
pin should be filtered with 0.01uf capacitor.
2. Output is enabled if OE pin is floated or not connected.
3. t
su
is time to 100PPM stable output frequency after V
DD
is applied and outputs are enabled.
4. Output Waveform and Connection Diagram define the parameters.
5. Period Jitter includes crosstalk from adjacent output.
6. Contact
Sales@Discera.com
for alternate output options (LVPECL, LVDS, LVCMOS).
7. Contact
Sales@Discera.com
for alternative frequency options
_____________________________________________________________________________________________________________________________ _________________
DSC512-05
Page 2
DSC512-05
Crystal-less™ Four Output Clock Generator
Absolute Maximum Ratings
Item
Supply Voltage
Input Voltage
Junction Temp
Storage Temp
Soldering Temp
ESD
HBM
MM
CDM
Min
-0.3
-0.3
-
-55
-
-
Max
+4.0
V
DD
+0.3
+150
+150
+260
4000
400
1500
Unit
V
V
°C
°C
°C
V
Condition
40sec max.
Solder Reflow Profile
20-40
Sec
Temperature (°C)
217
°
C
200
°
C
.
ax
3C
/
Se
cM
ax
60-150
Sec
260
°
C
.
S
6C/
6C/
6C/
c
c
ec
Ma
Ma
Ma
150
°
C
3C
/
Se
60-180
Sec
cM
Reflow
.
.
x.
Pre heat
8 min max
Cool
Time
25
°
C
20 QFN
MSL 1 @ 260°C refer to JSTD-020C
Ramp-Up Rate (200°C to Peak Temp)
3°C/Sec Max.
Preheat Time 150°C to 200°C
60-180 Sec
Time maintained above 217°C
60-150 Sec
Peak Temperature
255-260°C
Time within 5°C of actual Peak
20-40 Sec
Ramp-Down Rate
6°C/Sec Max.
Time 25°C to Peak Temperature
8 min Max.
_____________________________________________________________________________________________________________________________ _________________
DSC512-05
Page 3
DSC512-05
Crystal-less™ Four Output Clock Generator
Pin Description (20 QFN)
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin Name
OE1
NC
VSS
VSS
CLK0-
CLK0+
CLK1-
CLK1+
VDD
NC
OE2
NC
VSS
VSS
CLK2-
CLK2+
CLK3-
CLK3+
VDD
NC
Pin Type
I
NA
Power
Power
O
O
O
O
Power
NA
I
NA
Power
Power
O
O
O
O
Power
NA
Description
Output Enable; active high – See Table 1
Leave unconnected or grounded
Ground
Ground
Complement output of differential pair – This output is
turned off when LVCMOS format is configured
True output of differential pair or LVCMOS output (14MHz)
Complement output of differential pair (50MHz)
True output of differential pair (50MHz)
Power Supply
Leave unconnected or grounded
Output Enable; active high – See Table 1
Leave unconnected or grounded
Ground
Ground
Complement output of differential pair (50MHz)
True output of differential pair (50MHz)
Complement output of differential pair – This output is
turned off when LVCMOS format is configured
True output of differential pair or LVCMOS output (16MHz)
Power Supply
Leave unconnected or grounded
_____________________________________________________________________________________________________________________________ _________________
DSC512-05
Page 4
DSC512-05
Crystal-less™ Four Output Clock Generator
Pin Diagram (20
QFN)
CLK3+
CLK2+
16
CLK3-
20
OE1
NC
VSS
VSS
1
2
3
4
5
19
18
17
15
14
13
12
11
VSS
VSS
NC
OE2
6
7
8
9
10
CLK0+
CLK1+
CLK0-
CLK1-
20 QFN 5.0 x 3.2mm
Connection Diagram (20 QFN; 2 LVDS and 2 LVCMOS outputs)
_____________________________________________________________________________________________________________________________ _________________
DSC512-05
Page 5
VDD
NC
CLK2-
VDD
NC
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
