54ACT16841, 74ACT16841
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS174A – MAY 1991 – REVISED APRIL 1996
D
D
D
D
D
D
D
D
D
Members of the Texas Instruments
Widebus
™
Family
Inputs Are TTL-Voltage Compatible
3-State Outputs Drive Bus Lines Directly
Provide Extra Bus Driving/Latches
Necessary for Wider Address/Data Paths or
Buses With Parity
Flow-Through Architecture Optimizes
PCB Layout
Distributed V
CC
and GND Pin Configuration
Minimizes High-Speed Switching Noise
EPIC
™
(Enhanced-Performance Implanted
CMOS) 1-µm Process
500-mA Typical Latch-Up Immunity at
125°C
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) Packages,
300-mil Shrink Small-Outline (DL) Packages
Using 25-mil Center-to-Center Pin
Spacings, and 380-mil Fine-Pitch Ceramic
Flat (WD) Packages Using 25-mil
Center-to-Center Pin Spacings
54ACT16841 . . . WD PACKAGE
74ACT16841 . . . DGG OR DL PACKAGE
(TOP VIEW)
description
These 20-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The ’ACT16841 can be used as two 10-bit latches
or one 20-bit latch. The 20 latches are transparent
D-type. While the latch-enable (1LE or 2LE) input
is high, the Q outputs of the corresponding 10-bit
latch follow the data (D) inputs. When LE is taken
low, the Q outputs are latched at the levels that
were set up at the D inputs.
1OE
1Q1
1Q2
GND
1Q3
1Q4
V
CC
1Q5
1Q6
1Q7
GND
1Q8
1Q9
1Q10
2Q1
2Q2
2Q3
GND
2Q4
2Q5
2Q6
V
CC
2Q7
2Q8
GND
2Q9
2Q10
2OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1LE
1D1
1D2
GND
1D3
1D4
V
CC
1D5
1D6
1D7
GND
1D8
1D9
1D10
2D1
2D2
2D3
GND
2D4
2D5
2D6
V
CC
2D7
2D8
GND
2D9
2D10
2LE
A buffered output-enable (1OE or 2OE) input can be used to place the outputs of the corresponding 10-bit latch
in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state,
the outputs neither load nor drive the bus lines significantly.
OE does not affect the internal operation of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
Copyright
©
1996, Texas Instruments Incorporated
•
DALLAS, TEXAS 75265
1
54ACT16841, 74ACT16841
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS174A – MAY 1991 – REVISED APRIL 1996
description (continued)
The 74ACT16841 is packaged in TI’s shrink small-outline package (DL), which provides twice the I/O pin count
and functionality of standard small-outline packages in the same printed-circuit-board area.
The 54ACT16841 is characterized for operation over the full military temperature range of –55°C to 125°C. The
74ACT16841 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 10-bit latch)
INPUTS
OE
L
L
L
H
LE
H
H
L
X
D
H
L
X
X
OUTPUT
Q
H
L
Q0
Z
logic symbol
†
1
1OE
1LE
2OE
2LE
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
1D9
1D10
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2D9
2D10
56
28
29
55
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
30
3D
4
EN2
C1
EN4
C3
1D
2
2
3
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
27
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
1Q9
1Q10
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
2Q9
2Q10
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303
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DALLAS, TEXAS 75265
54ACT16841, 74ACT16841
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS174A – MAY 1991 – REVISED APRIL 1996
logic diagram (positive logic)
1OE
1LE
1
56
C1
1D1
55
1D
2
1Q1
2D1
2OE
2LE
28
29
C1
42
1D
15
2Q1
To Nine Other Channels
To Nine Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
CC
+ 0.5 V
Output voltage range, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
CC
+ 0.5 V
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50
mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50
mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±500
mA
Maximum package power dissipation at T
A
= 55°C (in still air) (see Note 2): DGG package . . . . . . . . . . 1 W
DL package . . . . . . . . . . . 1.4 W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150
_
C and a board trace length of 750 mils.
recommended operating conditions (see Note 3)
54ACT16841
MIN
VCC
VIH
VIL
VI
VO
IOH
IOL
∆t/∆v
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
Output voltage
High-level output current
Low-level output current
Input transition rise or fall rate
0
–55
0
0
4.5
2
0.8
VCC
VCC
–24
24
10
125
0
–40
0
0
NOM
5
MAX
5.5
74ACT16841
MIN
4.5
2
0.8
VCC
VCC
–24
24
10
85
NOM
5
MAX
5.5
UNIT
V
V
V
V
V
mA
mA
ns/V
°C
TA
Operating free-air temperature
NOTE 3: Unused inputs must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
54ACT16841, 74ACT16841
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS174A – MAY 1991 – REVISED APRIL 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = –50
µA
50
VOH
IOH = –24 mA
24
IOH = –75 mA†
IOL = 50
µA
VOL
IOL = 24 mA
IOL = 75 mA†
VI = VCC or GND
VO = VCC or GND
VI = VCC or GND,
IO = 0
VCC
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5V
5V
3
11
±0.1
±0.5
8
0.9
0.1
0.1
0.36
0.36
TA = 25°C
MIN
TYP
MAX
4.4
5.4
3.94
4.94
54ACT16841
MIN
4.4
5.4
3.8
4.8
3.85
0.1
0.1
0.44
0.44
1.65
±1
±5
80
1
MAX
74ACT16841
MIN
4.4
5.4
3.8
4.8
3.85
0.1
0.1
0.44
0.44
1.65
±1
±5
80
1
µA
µA
µA
mA
pF
pF
V
V
MAX
UNIT
II
IOZ
ICC
∆I
CC‡
Ci
Co
One input at 3.4 V,
Other inputs at VCC or GND
VI = VCC or GND
VO = VCC or GND
† Not more than one output should be tested at a time, and the duration of the test should not exceed 10 ms.
‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
timing requirements over recommended operating free-air temperature range,
V
CC
= 5 V
±
0.5 V (unless otherwise noted) (see Figure 1)
TA = 25°C
MIN
MAX
tw
tsu
th
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
time
High
Low
4
1.5
3
4.5
54ACT16841
MIN
4
1.5
3
4.5
MAX
74ACT16841
MIN
4
1.5
3
4.5
MAX
UNIT
ns
ns
ns
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
±
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
FROM
(INPUT)
D
LE
TO
(OUTPUT)
Q
Q
Q
Q
TA = 25°C
MIN
TYP
MAX
4
3.2
4.5
4.3
3.1
3.8
4
4
7.1
6.9
7.7
7.8
6.4
7.6
7.3
6.8
10.3
11
11.3
11.4
10.1
12.1
9.5
8.9
54ACT16841
MIN
4
3.2
4.5
4.3
3.1
3.8
4
4
MAX
11.8
12.2
12.7
12.7
11.3
13.7
10.2
9.6
74ACT16841
MIN
4
3.2
4.5
4.3
3.1
3.8
4
4
MAX
11.8
12.2
12.7
12.7
11.3
13.7
10.2
9.6
UNIT
ns
ns
ns
ns
OE
OE
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
54ACT16841, 74ACT16841
20-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCAS174A – MAY 1991 – REVISED APRIL 1996
operating characteristics, V
CC
= 5 V, T
A
= 25
°
C
PARAMETER
Cpd
d
Power dissipation capacitance
Outputs enabled
Outputs disabled
TEST CONDITIONS
CL = 50 pF
pF,
f = 1 MHz
TYP
41
10
UNIT
pF
PARAMETER MEASUREMENT INFORMATION
2
×
VCC
From Output
Under Test
CL = 50 pF
(see Note A)
500
Ω
S1
Open
GND
500
Ω
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
Open
2
×
VCC
GND
LOAD CIRCUIT
Timing Input
(see Note B)
tw
3V
Input
1.5 V
1.5 V
0V
VOLTAGE WAVEFORMS
3V
Input
tPLH
In-Phase
Output
tPHL
Out-of-Phase
Output
50% VCC
50% VCC
1.5 V
1.5 V
0V
tPHL
VOH
50% VCC
VOL
tPLH
VOH
50% VCC
VOL
Output
Waveform 2
S1 at GND
(see Note B)
Output
Waveform 1
S1 at 2
×
VCC
(see Note B)
tPZH
Output
Control
(low-level
enabling)
VOLTAGE WAVEFORMS
Data Input
tsu
1.5 V
1.5 V
3V
0V
th
3V
1.5 V
0V
3V
1.5 V
tPZL
tPLZ
50% VCC
tPHZ
80% VCC
VOH
20% VCC
1.5 V
0V
[
VCC
VOL
50% VCC
[
0V
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR
≤
1 MHz, ZO = 50
Ω,
tr = 3 ns, tf = 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
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