TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170D –MARCH 1999 – REVISED JULY 2000
features
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
Fast Throughput Rate: 1.25 MSPS at 5 V,
625 KSPS at 3 V
Wide Analog Input: 0 V to AV
DD
Differential Nonlinearity Error: <
±
1 LSB
Integral Nonlinearity Error: <
±
1 LSB
8-to-1 Analog MUX – TLV1578
Internal OSC
Single 2.7-V to 5.5-V Supply Operation
Low Power: 12 mW at 3 V and 35 mW at 5 V
Auto Power Down of 1 mA Max
Software Power Down: 10
µA
Max
Hardware Configurable
DSP and Microcontroller Compatible
Parallel Interface
Binary/Twos Complement Output
Hardware Controlled Extended Sampling
Channel Sweep Mode Operation and
Channel Select
Hardware or Software Start of Conversion
TLV1578
DA PACKAGE
(TOP VIEW)
CH0
CH1
CH2
CH3
CS
WR
RD
CLK
DGND
DVDD
INT/EOC
D0
D1
D2
D3
D4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
CH7
CH6
CH5
CH4
MO
AIN
AVDD
AGND
REFM
REFP
CSTART
D9/A1
D8/A0
D7
D6
D5
TLV1571
DW OR PW PACKAGE
(TOP VIEW)
CS
WR
RD
CLK
DGND
DVDD
INT/EOC
D0
D1
D2
D3
D4
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
applications
Mass Storage and HDD
Automotive
Digital Servos
Process Control
General-Purpose DSP
Image Sensor Processing
NC
AIN
AVDD
AGND
REFM
REFP
CSTART
D9/A1
D8/A0
D7
D6
D5
NC – No internal connection
description
The TLV1571/1578 is a 10-bit data acquisition system that combines an 8-channel input multiplexer (MUX), a
high-speed 10-bit ADC, and a parallel interface. The device contains two on-chip control registers allowing
control of channel selection, software conversion start, and power down via the bidirectional parallel port. The
control registers can be set to a default mode by applying a dummy RD signal when WR is tied low. This allows
the TLV1571/1578 to be configured by hardware. The MUX is independently accessible. This allows the user to
insert a signal conditioning circuit such as an antialiasing filter or an amplifier, if required, between the MUX and
the ADC. Therefore, one signal conditioning circuit can be used for all eight channels. The TLV1571 is a single
channel analog input device with all the same functions as the TLV1578.
The TLV1571/TLV1578 operates from a single 2.7-V to 5.5-V power supply. It accepts an analog input range
from 0 V to AV
DD
and digitizes the input at a maximum 1.25 MSPS throughput rate at 5 V. The power dissipations
are only 12 mW with a 3-V supply or 35 mW with a 5-V supply. The device features an auto power-down mode
that automatically powers down to 1 mA 50 ns after conversion is performed. In software power-down mode, the
ADC is further powered down to only 10
µA.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
©
2000, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
1
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170D –MARCH 1999 – REVISED JULY 2000
description (continued)
Very high throughput rate, simple parallel interface, and low power consumption make the TLV1571/TLV1578
an ideal choice for high-speed digital signal processing requiring multiple analog inputs.
AVAILABLE OPTIONS
PACKAGE
TA
0°C to 70°C
– 40°C to 85°C
32 TSSOP
(DA)
TLV1578CDA
TLV1578IDA
24 SOP
(DW)
TLV1571CDW
TLV1571IDW
24 TSSOP
(PW)
TLV1571CPW
TLV1571IPW
functional block diagram – TLV1571/78
MO
AVDD AIN
REFP
REFM
DVDD
CH0 – CH7
MUX
TLV1578 Only
Internal
Clock
10-BIT
SAR ADC
Three
State
Latch
D0 – D7
D8/A0
D9/A1
MUX
CLK
CS
RD
WR
CSTART
Input Registers
and Control Logic
INT/EOC
AGND
DGND
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170D –MARCH 1999 – REVISED JULY 2000
Terminal Functions
TERMINAL
NO.
TLV1571
21
23
22
–
4
1
18
5
6
8 –12,
13 –15
16
17
7
TLV1578
25
27
26
1– 4,
29–32
8
5
22
9
10
12 –16,
17–19
20
21
11
28
24
3
20
19
2
7
24
23
6
I
I
I
I
I/O
I/O
I/O
O
O
I
I
I
I
I
Analog ground
ADC analog input (used as single analog input channel for TLV1571)
Analog supply voltage, 2.7 V to 5.5 V
Analog input channels
External clock input
Chip select. A logic low on CS enables the TLV1571/ TLV1578.
Hardware sample and conversion start input. The falling edge of CSTART starts sampling and
the rising edge of CSTART starts conversion.
Digital ground
Digital supply voltage, 2.7 V to 5.5 V
Bidirectional 3-state data bus
Bidirectional 3-state data bus. D8/A0 along with D9/A1 is used as address lines to access CR0
and CR1 for initialization.
Bidirectional 3-state data bus. D9/A1 along with D8/A0 is used as address lines to access CR0
and CR1 for initialization.
End-of-conversion/interrupt
On-chip MUX analog output
Not connected
Read data. A falling edge on RD enables a read operation on the data bus when CS is low.
Lower reference voltage (nominally ground). REFM must be supplied or REFM pin must be
grounded.
Upper reference voltage (nominally AVDD). The maximum input voltage range is determined by
the difference between the voltage applied to REFP and REFM.
Write data. A rising edge on the WR latches in configuration data when CS is low. When using
software conversion start, a rising edge on WR also initiates an internal sampling start pulse.
When WR is tied to ground, the ADC in nonprogrammable (hardware configuration mode).
I/O
DESCRIPTION
NAME
AGND
AIN
AVDD
CH0 – CH7
CLK
CS
CSTART
DGND
DVDD
D0 – D7
D8/A0
D9/A1
INT/EOC
MO
NC
RD
REFM
REFP
WR
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170D –MARCH 1999 – REVISED JULY 2000
detailed description
Ain
Charge
Redistribution
DAC
_
+
SAR
Register
ADC Code
REFM
Control
Logic
Figure 1. Analog-to-Digital SAR Converter
The TLV1571/78 is a successive-approximation ADC utilizing a charge redistribution DAC. Figure 1 shows a
simplified version of the ADC.
The sampling capacitor acquires the signal on AIN during the sampling period. When the conversion process
starts, the SAR control logic and charge redistribution DAC are used to add and subtract fixed amounts of charge
from the sampling capacitor to bring the comparator into a balanced condition. When the comparator is
balanced, the conversion is complete and the ADC output code is generated.
sampling frequency, f
s
The TLV1571/TLV1578 requires 16 CLKs for each conversion, (assuming the read cycle takes 1 CLK). The
equivalent maximum sampling frequency achievable with a given CLK frequency is:
f
s(max)
= (1/17) f
CLK
The TLV1571 and TLV1578 are software configurable. The first two MSB bits, D(9,8) are used to address which
register to set. The rest of the eight bits are used as control data bits. There are two control registers, CR0 and
CR1, that are user configurable. All of the register bits are written to the control register during write cycles. A
description of the control registers is shown in Figure 2.
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
TLV1571, TLV1578
2.7 V TO 5.5 V, 1-/8-CHANNEL, 10-BIT,
PARALLEL ANALOG-TO-DIGITAL CONVERTERS
SLAS170D –MARCH 1999 – REVISED JULY 2000
detailed description (continued)
control registers
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
A(1:0)=00
Control Register Zero (CR0)
D7
D6
D5
STARTSEL PROGEOC CLKSEL
D4
SWPWDN
D3
MODESEL
D2
D1
CHSEL(2–0)†
D0
0:
0:
HARDWARE INT
START
(CSTART)
1:
EOC
1:
SOFTWARE
START
0:
Internal
Clock
0:
NORMAL
1:
Power
Down
1:
External
Clock
0:
Single
Channel
1:
Sweep
Mode
D(2– 0)
0h
1h
2h
3h
4h
5h
6h
7h
Single
Input
0
1
2
3
4
5
6
7
Channels Swept
0,1
0,1,2,3
0,1,2,3,4,5,
0,1,2,3,4,5,6,7
N/A
N/A
N/A
N/A
A(1:0)=01
Control Register One (CR1)
D7‡
D6
D3
D5‡
D4‡
RESERVED OSCSPD 0 Reserved 0 Reserved OUTCODE
D2
READREG
D1
STEST1
D0
STEST0
0:
Reserved
Bit
Always
Write 0
0:
INT. OSC.
SLOW
1:
INT. OSC.
FAST
0:
Reserved
Bit
Always
Write 0
0:
Reserved
Bit,
Always
Write 0
0:
Binary
0:
Enable Self
Test
1:
1:
Enable
2s
Register
Complement Read back
CR1.(1–0)
0h
1h
2h
3h
0h
1h
2h
3h
IF READREG = 0
ACTION
Output =
CONVERSION result
Output =
SELF TEST 1 result
Output =
SELF TEST 2 result
Output =
SELF TEST 3 result
IF READREG = 1
Output Contents of
CR0
Output Contents of
CR1
RESERVED
RESERVED
† Don’t care for TLV1571
‡ When in read back mode, the values read from the control register reserved bits are don’t care.
Figure 2. Input Data Format
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
