®
RIVA 128ZX™
128-BIT 3D MULTIMEDIA ACCELERATOR
PRELIMINARY DATA
KEY FEATURES
•
Fast 32-bit VGA/SVGA
•
High performance 128-bit 2D/GUI/DirectDraw
Acceleration
•
Interactive, Photorealistic Direct3D Accelera-
tion with advanced effects
•
Pinout backwards compatible with RIVA 128
•
Massive 1.6Gbytes/s, 100MHz 128-bit wide
8MByte SGRAM framebuffer interface
•
Adds 16Mbit SDRAM support for cost sensitive
8MByte framebuffer applications
•
Video Acceleration for DirectDraw/DirectVideo,
MPEG-1/2 and Indeo
®
- Planar 4:2:0 and packed 4:2:2 Color Space
Conversion
- X and Y smooth up and down scaling
•
250MHz Palette-DAC supporting up to
1600x1200@85Hz
•
NTSC and PAL output with flicker-filter
•
Multi-function Video Port and serial interface
BLOCK DIAGRAM
•
Bus mastering DMA Accelerated Graphics Port
(AGP) 1.0 Interface supporting 133MHz 2X
data transfer mode
•
Bus mastering DMA PCI 2.1 interface
•
ACPI power management interface support
•
0.35 micron 5LM CMOS
•
300 PBGA
DESCRIPTION
The RIVA128ZX™ offers unparalleled 2D and 3D
performance, meeting all the requirements of the
mainstream PC graphics market and Microsoft’s
PC’97. RIVA128ZX combines all the features of
RIVA 128 plus 8MByte SDRAM and SGRAM
based framestore support and AGP 2X data trans-
fer. It provides the most advanced Direct3D™ ac-
celeration solution and delivers leadership VGA,
2D and Video performance, enabling a range of
applications from 3D games through to DVD, In-
tercast™ and video conferencing.
1.6 GByte/s
Internal Bus
Bandwidth
DMA Bus
Video Port
DMA Engine
CCIR656
Video
PCI/AGP
Host
Interface
FIFO/
DMA
Pusher
Graphics Engine
128 bit 2D
Direct3D
DMA Engine
Internal Bus
Palette DAC
YUV - RGB,
X & Y scaler
8MByte
SDRAM/SGRAM
Interface
Monitor/
TV
VGA
128 bit
interface
June 1998
The information in this datasheet is subject to change
7071857 00
1/85
RIVA128ZX
128-BIT 3D MULTIMEDIA ACCELERATOR
TABLE OF CONTENTS
1
2
RIVA128ZX 300PBGA DEVICE PINOUT.......................................................................................
PIN DESCRIPTIONS ......................................................................................................................
2.1 ACCELERATED GRAPHICS PORT (AGP) INTERFACE .....................................................
2.2 PCI 2.1 LOCAL BUS INTERFACE ........................................................................................
2.3 FRAMEBUFFER INTERFACE ..............................................................................................
2.4 VIDEO PORT.........................................................................................................................
2.5 DEVICE ENABLE SIGNALS ..................................................................................................
2.6 DISPLAY INTERFACE ..........................................................................................................
2.7 VIDEO DAC AND PLL ANALOG SIGNALS ..........................................................................
2.8 POWER SUPPLY ..................................................................................................................
2.9 TEST......................................................................................................................................
OVERVIEW OF THE RIVA128ZX ..................................................................................................
3.1 BALANCED PC SYSTEM......................................................................................................
3.2 HOST INTERFACE ...............................................................................................................
3.3 2D ACCELERATION .............................................................................................................
3.4 3D ENGINE ...........................................................................................................................
3.5 VIDEO PROCESSOR............................................................................................................
3.6 VIDEO PORT.........................................................................................................................
3.7 DIRECT RGB OUTPUT TO LOW COST PAL/NTSC ENCODER .........................................
3.8 SUPPORT FOR STANDARDS..............................................................................................
3.9 RESOLUTIONS SUPPORTED..............................................................................................
3.10 CUSTOMER EVALUATION KIT ............................................................................................
3.11 TURNKEY MANUFACTURING PACKAGE ...........................................................................
ACCELERATED GRAPHICS PORT (AGP) INTERFACE .............................................................
4.1 RIVA128ZX AGP INTERFACE ..............................................................................................
4.2 AGP BUS TRANSACTIONS..................................................................................................
PCI 2.1 LOCAL BUS INTERFACE.................................................................................................
5.1 RIVA128ZX PCI INTERFACE ...............................................................................................
5.2 PCI TIMING SPECIFICATION ...............................................................................................
FRAMEBUFFER INTERFACE .......................................................................................................
6.1 SDRAM INTERFACE ............................................................................................................
6.2 SGRAM INTERFACE ............................................................................................................
6.3 SDRAM/SGRAM ACCESSES AND COMMANDS ................................................................
6.4 LAYOUT OF FRAMEBUFFER CLOCK SIGNALS ................................................................
6.5 FRAMEBUFFER INTERFACE TIMING SPECIFICATION ....................................................
VIDEO PLAYBACK ARCHITECTURE...........................................................................................
7.1 VIDEO SCALER PIPELINE ...................................................................................................
VIDEO PORT ..................................................................................................................................
8.1 VIDEO INTERFACE PORT FEATURES ...............................................................................
8.2 BI-DIRECTIONAL MEDIA PORT POLLING COMMANDS USING MPC ..............................
8.3 TIMING DIAGRAMS ..............................................................................................................
8.4 656 MASTER MODE .............................................................................................................
8.5 VBI HANDLING IN THE VIDEO PORT .................................................................................
8.6 SCALING IN THE VIDEO PORT ...........................................................................................
BOOT ROM INTERFACE...............................................................................................................
4
5
5
5
7
7
8
8
8
8
9
10
10
10
11
11
11
12
12
12
12
13
13
14
15
15
23
23
24
30
31
32
35
37
37
42
43
45
45
46
47
51
52
52
53
3
4
5
6
7
8
9
2/85
128-BIT 3D MULTIMEDIA ACCELERATOR
10
11
RIVA128ZX
55
57
57
57
58
59
60
61
63
63
63
64
64
64
64
65
65
66
67
67
68
68
69
69
69
POWER-ON RESET CONFIGURATION........................................................................................
DISPLAY INTERFACE ...................................................................................................................
11.1 PALETTE-DAC ......................................................................................................................
11.2 PIXEL MODES SUPPORTED ...............................................................................................
11.3 HARDWARE CURSOR .........................................................................................................
11.4 SERIAL INTERFACE.............................................................................................................
11.5 ANALOG INTERFACE ..........................................................................................................
11.6 TV OUTPUT SUPPORT ........................................................................................................
IN-CIRCUIT BOARD TESTING ......................................................................................................
12.1 TEST MODES .......................................................................................................................
12.2 CHECKSUM TEST ................................................................................................................
ELECTRICAL SPECIFICATIONS ..................................................................................................
13.1 ABSOLUTE MAXIMUM RATINGS ........................................................................................
13.2 OPERATING CONDITIONS ..................................................................................................
13.3 DC SPECIFICATIONS...........................................................................................................
13.4 ELECTRICAL SPECIFICATIONS ..........................................................................................
13.5 DAC CHARACTERISTICS ....................................................................................................
13.6 FREQUENCY SYNTHESIS CHARACTERISTICS ................................................................
PACKAGE DIMENSION SPECIFICATION ....................................................................................
14.1 300 PIN BALL GRID ARRAY PACKAGE ..............................................................................
REFERENCES................................................................................................................................
12
13
14
15
16 ORDERING INFORMATION ..........................................................................................................
APPENDIX ...............................................................................................................................................
A
PCI CONFIGURATION REGISTERS .............................................................................................
A.1 REGISTER DESCRIPTIONS FOR PCI CONFIGURATION SPACE ....................................
3/85
1
NOTES
RIVA128ZX
4/85
4
FBD[17]
FBD[19]
FBD[21]
FBD[23]
FBDQM[2]
FBA[0]
FBA[2]
FBA[4]
FBA[6]
FBA[8]
FBDQM[5]
FBD[41]
FBD[43]
FBD[45]
FBD[47]
FBD[56]
FBD[57]
1
2
3
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
RIVA128ZX 300PBGA DEVICE PINOUT
1
2
∗
FBD[18]
FBD[20]
FBD[22]
FBDQM[0]
FBA[9]
FBA[1]
FBA[3]
FBA[5]
FBA[7]
FBCLK1
FBDQM[7]
FBD[40]
FBD[42]
FBD[44]
FBD[46]
FBD[58]
FBD[59]
FBD[27]
FBD[26]
FBD[25]
FBD[15]
FBD[13]
FBD[11]
FBD[9]
FBDQM[1]
FBWE#
FBRAS#
FBA[10]
FBDQM[4]
FBD[55]
FBD[54]
FBD[53]
FBD[60]
FBD[61]
FBD[30]
VDD
FBD[24]
FBD[14]
FBD[12]
FBD[10]
FBD[8]
FBDQM[3]
FBCAS#
FBCS0
FBCS1
FBDQM[6]
VDD
FBD[52]
FBD[51]
FBD[62]
FBD[63]
VDD
NIC
VDD
VDD
VDD
A
FBD[4]
FBD[6]
FBD[7]
B
FBD[3]
FBD[5]
FBD[16]
C
FBD[1]
FBD[2]
FBD[28]
D
FBCKE
∗
VDD
VDD
VDD
VDD
FBCLK0
FBD[0]
FBD[29]
E
FBCLKFB
VDD
VDD
FBD[48]
SCL
FBCLK2
FBD[31]
FBD[50]
FBD[39]
FBD[38]
F
MP_AD[4]
MPCLAMP
VDD
MP_AD[6]
NIC
SDA
FBD[49]
FBD[37]
FBD[36]
G
MP_AD[3]
VDD
MPFRAME# MP_AD[7]
MP_AD[5]
FBD[35]
FBD[34]
FBD[33]
FBD[32]
H
MP_AD[0]
GND
GND
GND
GND
MP_AD[2]
MPSTOP#
MPCLK
NIC
FBDQM[12] FBDQM[14] FBDQM[15] FBDQM[13]
J
GND
GND
GND
GND
FBDQM[8] MPDTACK# MP_AD[1]
FBD[118]
FBD[119]
FBD[105]
FBD[104]
K
FBD[73]
GND
GND
GND
GND
FBDQM[9]
FBD[87]
FBDQM[10] FBDQM[11]
FBD[116]
FBD[117]
FBD[107]
FBD[106]
L
FBD[75]
GND
GND
GND
GND
FBD[86]
FBD[85]
FBD[72]
FBD[114]
FBD[115]
FBD[109]
FBD[108]
M
FBD[77]
NIC
FBD[84]
FBD[83]
FBD[74]
FBD[112]
FBD[113]
FBD[111]
FBD[110]
N
FBD[79]
VDD
FBD[82]
FBD[81]
FBD[76]
NIC
FBD[102]
FBD[103]
FBD[121]
FBD[120]
P
FBD[89]
NIC
FBD[80]
FBD[71]
FBD[78]
VDD
FBD[100]
FBD[101]
FBD[123]
FBD[122]
R
VDD
NIC
HOSTVDD HOSTVDD
HOST-
CLAMP
FBD[70]
FBD[69]
FBD[88]
NIC
FBD[98]
FBD[99]
FBD[125]
FBD[124]
T
FBD[91]
HOST-
CLAMP
XTALOUT
PCIRST#
AGPST[1]
FBD[68]
FBD[67]
FBD[90]
HOSTVDD
HOST-
CLAMP
HOSTVDD
HOST-
CLAMP
VDD
FBD[97]
FBD[127]
FBD[126]
U
DACVDD
VREF
PCIINTA#
PCIGNT#
FBD[66]
FBD[65]
FBD[92]
PCIAD[30] PCIAD[26] PCICBE#[3] PCIAD[20] PCIAD[16] PCITRDY#
PCIPAR
HOSTVDD PCICBE#[0]
FBD[96]
VIDVSYNC VIDHSYNC
V
COMP
PLLVDD
PCIREQ#
AGPST[2]
FBD[64]
FBD[95]
RED
AGPPIPE# PCIAD[28] PCIAD[24] PCIAD[22]
PCIAD[18] PCIFRAME# PCISTOP# PCIAD[15] PCIAD[11]
PCIAD[6]
PCIAD[2] TESTMODE ROMCS#
W
XTALIN
PCICLK
AGPST[0]
FBD[93]
FBD[94]
BLUE
PCIAD[31] PCIAD[27]
AGPAD-
STB1
PCIAD[21]
PCIAD[17]
PCIIRDY# PCICBE#[1] PCIAD[13]
PCIAD[9]
PCIAD[4]
PCIAD[0]
PCIAD[7]
PCIAD[5]
NIC = No Internal Connection. Do not connect to these pins.
VDD=3.3V
Signals denoted with an asterisk are defined for future expansion. See
Pin Descriptions,
Section 2, page 5 for details.
PCIIDSEL/
PCI-
PCIAD[29] PCIAD[25] PCIAD[23] PCIAD[19] PCICBE#[2]
AGPRBF#
DEVSEL#
PCIAD[14] PCIAD[12] PCIAD[10]
PCIAD[8]
AGPAD-
STB0
PCIAD[3]
PCIAD[1]
128-BIT 3D MULTIMEDIA ACCELERATOR
Y
GREEN
GND
RSET
128-BIT 3D MULTIMEDIA ACCELERATOR
2
2.1
PIN DESCRIPTIONS
ACCELERATED GRAPHICS PORT (AGP) INTERFACE
I/O
I
Description
RIVA128ZX
Signal
AGPST[2:0]
AGP status bus providing information from the arbiter to the RIVA128ZX on what it may
do.
AGPST[2:0]
only have meaning to the RIVA128ZX when
PCIGNT#
is asserted. When
PCIGNT#
is de-asserted these signals have no meaning and must be ignored.
000
001
010
011
100
101
110
111
Indicates that previously requested low priority read or flush data is being
returned to the RIVA128ZX.
Indicates that previously requested high priority read data is being returned to
the RIVA128ZX.
Indicates that the RIVA128ZX is to provide low priority write data for a previous
enqueued write command.
Indicates that the RIVA128ZX is to provide high priority write data for a previous
enqueued write command.
Reserved
Reserved
Reserved
Indicates that the RIVA128ZX has been given permission to start a bus transac-
tion. The RIVA128ZX may enqueue AGP requests by asserting
AGPPIPE#
or
start a PCI transaction by asserting
PCIFRAME#. AGPST[2:0]
are always an
output from the Core Logic (AGP chipset) and an input to the RIVA128ZX.
AGPRBF#
O
Read Buffer Full indicates when the RIVA128ZX is ready to accept previously requested
low priority read data or not. When
AGPRBF#
is asserted the arbiter is not allowed to
return (low priority) read data to the RIVA128ZX. This signal should be pulled up via a
4.7KΩ resistor (although it is supposed to be pulled up by the motherboard chipset).
Pipelined Read is asserted by RIVA128ZX (when the current master) to indicate a full
width read address is to be enqueued by the target. The RIVA128ZX enqueues one
request each rising clock edge while
AGPPIPE#
is asserted. When
AGPPIPE#
is de-
asserted no new requests are enqueued across
PCIAD[31:0]. AGPPIPE#
is a sustained
tri-state signal from the RIVA128ZX and is an input to the target (the core logic).
Bus strobe signals providing timing for AGP 2X data transfer mode on
PCIAD[15:00]
and
PCIAD[31:16]
respectively. The agent that is supplying data drives these signals.
AGPPIPE#
O
AGPADSTB0,
AGPADSTB1
I/O
2.2
PCI 2.1 LOCAL BUS INTERFACE
I/O
I
Description
PCI clock. This signal provides timing for all transactions on the PCI bus, except for
PCIRST#
and
PCIINTA#.
All PCI signals are sampled on the rising edge of
PCICLK
and
all timing parameters are defined with respect to this edge .
PCI reset. This signal is used to bring registers, sequencers and signals to a consistent
state. When
PCIRST#
is asserted all output signals are tristated.
32-bit multiplexed address and data bus. A bus transaction consists of an address phase
followed by one or more data phases.
Signal
PCICLK
PCIRST#
PCIAD[31:0]
I
I/O
5/85
stm32/stm8
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