PRELIMINARY
MX23L25640
256M-BIT NAND INTERFACE MASK ROM
DESCRIPTION
The MX23L25640 is a 256 Mbit NAND interface pro-
grammable mask read-only memory that operates with
a single power supply. The memory organization con-
sists of (512 + 16 (Redundancy)) bytes x 32 pages x
2,048 blocks.
The MX23L25640 is a serial type mask ROM in which
addresses and commands are input and data output
serially via the I/O pins.
The MX23L25640 is packed in 48-pin plastic TSOP(I)
and 44-pin TSOP.
FEATURES
• Word organization
- (33,554,432 + 1,048,576
Note
)words by 8 bits
• Page size
- (512 + 16
Note
) by 8 bits
• Block size
- (16,384 + 512
Note
) by 8 bits
Note :
Underlined parts are redundancy.
Caution Redundancy is not programmable parts and is
fixed to all FFH.
• Operation mode
- READ mode (1), READ mode (2), READ mode (3),
RESET, STATUS READ, ID READ
• Operating supply voltage : VCC = 3.3
±
0.3 V
• Access Time
- Memory cell array to starting address : 7 us (MAX.)
- Read cycle time : 50 ns (MAX.)
- RE access time : 35 ns (MAX.)
• Operating supply current
- During read : 30 mA (MAX.) (50 ns cycle operation)
- During standby (CMOS) : 100 uA (MAX.)
• Package Type
- 48-pin TSOP(I) (12mmx20mm)
- 44-pin TSOP
P/N:PM0802
REV. 1.7, JUN. 20, 2003
1
MX23L25640
BLOCK DIAGRAM
1 Page=528 Bytes
0
0
1
2
1 Block
=32 Pages
.
.
30
31
.
.
.
.
.
.
.
.
.
65,533
65,534
65,535
512 Bytes
(Main memory)
.
.
.
255 256
.
.
.
511
.
527
(A)
(B)
(C)
2,048 Blocks
=65,536 Pages
16 Bytes
(Redundancy)
•
The start address (SA) during read operation is specified divided into three areas using three types of read
commands.
- In read mode (1), start address (SA) is set in area (A).
- In read mode (2), start address (SA) is set in area (B).
- In read mode (3), start address (SA) is set in area (C).
One page consists of a total of 528 bytes broken down into 512 bytes (main memory) and 16 bytes (redundancy).
One block consists of 32 pages.
Caution The data of area (C) is redundancy. Redundancy is not programmable parts and is fixed to all FFH.
P/N:PM0802
REV. 1.7, JUN. 20, 2003
4
MX23L25640
Operation Modes
Command input, address input, and serial read are all performed from I/O pins, and the respective statuses are
controlled by the CLE, ALE, WE, RE, and CE signals.
Command
input cycle
Address input cycle
Serial read cycle
CLE
CE
WE
ALE
RE
I/O0~
I/O7
RB
Busy
Operation mode
Mode
Command input cycle
Address input cycle
Serial read cycle
CLE
H
L
L
ALE
L
H
L
CE
L
L
L
WE
RE
H
H
H
Operation mode during serial read
Mode
Data output
Output Hi-Z
Standby
Remark
´ : VIH or VIL
P/N:PM0802
REV. 1.7, JUN. 20, 2003
CLE
L
L
L
ALE
L
L
L
CE
L
L
H
WE
H
H
H
RE
L
H
x
I/O0 - I/O7
Data output
Hi-Z
Hi-Z
5
模拟与混合信号
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
