The documentation and process conversion measures
necessary to comply with this document shall be
completed by 22 May 2013.
INCH-POUND
MIL-PRF-19500/255Y
22 February 2013
SUPERSEDING
MIL-PRF-19500/255X
16 March 2011
PERFORMANCE SPECIFICATION SHEET
*
SEMICONDUCTOR DEVICE, TRANSISTOR, NPN, SILICON, SWITCHING,
TYPES 2N2221A, 2N2221AL, 2N2222A, 2N2222AL, 2N2221AUA, 2N2222AUA, 2N2221AUB, 2N2222AUB,
2N2221AUBC, AND 2N2222AUBC, 2N2221AUBN, 2N2222AUBN, 2N2221AUBCN, 2N2222AUBCN, JAN, JANTX,
JANTXV, JANTXVM, JANTXVD, JANTXVP, JANTXVL, JANTXVR, JANTXVF, JANTXVG, JANTXVH, JANS, JANSM,
JANSD, JANSP, JANSL, JANSR, JANSF, JANSG, JANSH, JANHC, JANHCM, JANHCD, JANHCP, JANHCL,
JANHCR, JANHCF, JANHCG, JANHCH, JANKC, JANKCM, JANKCD, JANKCP, JANKCL, JANKCR, JANKCF,
JANKCG, AND JANKCH
This specification is approved for use by all Departments
and Agencies of the Department of Defense.
The requirements for acquiring the product described herein shall consist of
this specification sheet and MIL-PRF-19500.
1. SCOPE
1.1 Scope. This specification covers the performance requirements for NPN, silicon, switching transistors. Five
levels of product assurance are provided for each encapsulated device type as specified in MIL-PRF-19500, and two
levels of product assurance are provided for each unencapsulated device type. Provisions for radiation hardness
assurance (RHA) to eight radiation levels is provided for JANTXV, JANS, JANHC, and JANKC product assurance
levels. RHA level designators “M”, “D”, “P“, “L”, “R”, “F’, “G” and “H” are appended to the device prefix to identify
devices, which have passed RHA requirements.
* 1.2 Physical dimensions. See figure 1 (similar to TO-18), figure 2 (surface mount case outline UA), figure 3
(surface mount case outlines UB, UBC, UBN, and UBCN), and figures 4, 5, and 6 (JANHC and JANKC).
*
1.3 Maximum ratings. Unless otherwise specified T
A
= +25°C.
Types
I
C
mA dc
All devices
800
V
CBO
V dc
75
V
CEO
V dc
50
V
EBO
V dc
6
T
J
and T
STG
°C
-65 to +200
* Comments, suggestions, or questions on this document should be addressed to DLA Land and Maritime,
ATTN: VAC, P.O. Box 3990, Columbus, OH 43218-3990, or emailed to
Semiconductor@dla.mil.
Since contact
information can change, you may want to verify the currency of this address information using the ASSIST
Online database at
https://assist.dla.mil
.
AMSC N/A
FSC 5961
MIL-PRF-19500/255Y
*
1.3 Maximum ratings. Unless otherwise specified T
A
= +25°C. - Continued.
P
T
T
A
= +25°C
(1) (2)
W
0.50
0.50
(4) 0.50
(4) 0.50
(4) 0.50
(4) 0.50
P
T
T
C
= +25°C
(1) (2)
W
1
1
N/A
N/A
N/A
N/A
P
T
T
SP(IS)
=
+25°C (1) (2)
W
N/A
N/A
1
1
1
1
P
T
T
SP(AM)
=
+25°C (1) (2)
W
N/A
N/A
1.5
1.5
N/A
N/A
R
θJA
(2) (3)
°C/W
325
325
(4) 325
(4) 325
(4) 325
(4) 325
R
θJC
(2) (3)
°C/W
150
150
N/A
N/A
N/A
N/A
R
θJSP(IS)
(2) (3)
°C/W
N/A
N/A
110
110
90
90
R
θJSP(AM)
(2) (3)
°C/W
N/A
N/A
40
40
N/A
N/A
Types
2N2221A, AL
2N2222A, AL
2N2221AUA
2N2222AUA
2N2221AUB, UBC,
UBN and UBCN
2N2222AUB, UBC,
UBN and UBCN
(1)
(2)
(3)
(4)
For derating, see figures 7, 8, 9, 10, and 11.
See 3.3 for abbreviations.
For thermal impedance curves, see figures 12, 13, 14, 15, and 16.
For non-thermal conductive PCB or unknown PCB surface mount conditions in free air, substitute figures 8
and 13 for the UA, UB, UC, UBN, and UBCN package and use R
θ
JA
.
*
1.4 Primary electrical characteristics. Unless otherwise specified, T
A
= +25°C.
h
FE
at V
CE
= 10 V dc
Limits
h
FE1
I
C
= 0. 1 mA dc
AL, UA, UB, UBC,
UBN, and UBCN
2N2221A, 2N2222A
30
50
h
FE2
I
C
= 1.0 mA dc
AL, UA, UB, UBC,
UBN, and UBCN
2N2221A, 2N2222A
35
150
Limit
75
325
/h
fe
/
f = 100 MHz
V
CE
= 20 V dc
I
C
= 20 mA dc
h
FE3
I
C
= 10 mA dc
AL, UA, UB, UBC,
UBN, and UBCN
2N2221A, 2N2222A
40
100
h
FE4
(1)
I
C
= 150 mA dc
AL, UA, UB, UBC,
UBN, and UBCN
2N2221A, 2N2222A
40
120
100
300
h
FE5
(1)
I
C
= 500 mA dc
AL, UA, UB, UBC,
UBN, and UBCN
2N2221A, 2N2222A
20
30
Min
Max
Types
C
obo
100 kHz
≤
f
≤
1 MHz
V
CB
= 10 V dc
I
E
= 0
pF
Switching (saturated)
t
on
See figure 17
ns
t
off
See figure 18
ns
2N2221A, 2N2222A
AL, UA, UB, UBC,
UBN, and UBCN
Types
Min
Max
2.5
8
35
300
Limit
V
CE(sat)1
(1)
I
C
= 150 mA dc
I
B
= 15 mA dc
V dc
V
CE(sat)2
(1)
I
C
= 500 mA dc
I
B
= 50 mA dc
V dc
V
BE(sat)1
(1)
I
C
= 150 mA dc
I
B
= 15 mA dc
V dc
0.6
1.2
V
BE(sat)2
(1)
I
C
= 500 mA dc
I
B
= 50 mA dc
V dc
2N2221A, 2N2222A
AL, UA, UB, UBC,
UBN, and UBCN
Min
Max
0.3
1.0
2.0
(1) Pulsed see 4.5.1.
2
MIL-PRF-19500/255Y
Symbol
CD
CH
HD
LC
LD
LL
LU
L
1
L
2
P
Q
TL
TW
r
α
Dimensions
Inches
Millimeters
Min
Max
Min
Max
.178
.195
4.52
4.95
.170
.210
4.32
5.33
.209
.230
5.31
5.84
.100 TP
2.54 TP
.016
.021
0.41
0.53
.500
.750
12.70 19.05
.016
.019
0.41
0.48
.050
1.27
.250
6.35
.100
2.54
.030
0.76
.028
.048
0.71
1.22
.036
.046
0.91
1.17
.010
0.25
45° TP
45° TP
1, 2, 9, 11, 12, 13
Note
6
7,8
7,8,13
7,8
7,8
7,8
5
3,4
3
10
6
NOTES:
1. Dimensions are in inches.
2. Millimeters are given for general information only.
3. Beyond r (radius) maximum, TL shall be held for a minimum length of .011 inch (0.28 mm).
4. Dimension TL measured from maximum HD.
5. Body contour optional within zone defined by HD, CD, and Q.
6. Leads at gauge plane .054 +.001 -.000 inch (1.37 +0.03 -0.00 mm) below seating plane shall be within .007
inch (0.18 mm) radius of true position (TP) at maximum material condition (MMC) relative to tab at MMC.
7. Dimension LU applies between L
1
and L
2
. Dimension LD applies between L
2
and LL minimum. Diameter
is uncontrolled in L
1
and beyond LL minimum.
8. All three leads.
9. The collector shall be internally connected to the case.
10. Dimension r (radius) applies to both inside corners of tab.
11. In accordance with ASME Y14.5M, diameters are equivalent to
φx
symbology.
12. Lead 1 = emitter, lead 2 = base, lead 3 = collector.
13. For L suffix devices, dimension LL = 1.5 inches (38.10 mm) min. and 1.75 inches (44.45 mm) max.
FIGURE 1. Physical dimensions (similar to TO-18).
3
MIL-PRF-19500/255Y
UA
Symbol
BL
BL2
BW
BW2
CH
L3
LH
LL1
LL2
LS
LW
LW2
*
Dimensions
Inches
Millimeters
Min
Max
Min
Max
.215
.225
5.46
5.71
.225
5.71
.145
.155
3.68
3.93
.155
3.93
.061
.075
1.55
1.90
.003
0.08
.029
.042
0.74
1.07
.032
.048
0.81
1.22
.072
.088
1.83
2.23
.045
.055
1.14
1.39
.022
.028
0.56
0.71
.006
.022
0.15
0.56
1
Collector
2
Emitter
3
Base
Note
3
5
5
4
N/C
Pin no.
Transistor
NOTES:
1. Dimensions are in inches.
2. Millimeters are given for general information only.
3. Dimension CH controls the overall package thickness. When a window lid is used, dimension CH must increase
by a minimum of .010 inch (0.254 mm) and a maximum of .040 inch (1.020 mm).
4. The corner shape (square, notch, radius) may vary at the manufacturer's option, from that shown on the
drawing.
* 5. Dimensions LW2 minimum and L3 minimum and the appropriate castellation length define an unobstructed
three-dimensional space traversing all of the ceramic layers in which a castellation was designed.
(Castellations are required on the bottom two layers, optional on the top ceramic layer.) Dimension LW2
maximum define the maximum width of the castellation at any point on its surface. Measurement of this
dimension may be made prior to solder dipping.
6. The co-planarity deviation of all terminal contact points, as defined by the device seating plane, shall not exceed
.006 inch (0.15mm) for solder dipped leadless chip carriers.
7. In accordance with ASME Y14.5M, diameters are equivalent to
φx
symbology.
* FIGURE 2. Physical dimensions, surface mount (UA version).
4
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