Freescale Semiconductor
Advance Information
Document Number: MC34931
Rev. 2.0, 10/2013
5.0 A H-bridge
The 34931 is a monolithic H-Bridge Power IC in a robust thermally
enhanced package. It is designed for any low voltage DC servo motor
control application within the current and voltage limits stated in this
specification. This device is powered by SMARTMOS technology.
The 34931 H-Bridge is able to control inductive loads with currents
up to 5.0 A peak. RMS current capability is subject to the degree of
heatsinking provided to the device package. Internal peak-current
limiting (regulation) is activated at load currents above 6.5 A ±1.5 A.
Output loads can be pulse-width modulated (PWM-ed) at frequencies
up to 11 kHz. A load current feedback feature provides a proportional
(0.24% of the load current) current output suitable for monitoring by a
microcontroller’s A/D input. A Status flag output reports undervoltage,
overcurrent, and overtemperature fault conditions.
Two independent inputs provide polarity control of two half-bridge
totem-pole outputs. The disable inputs are provided to force the H-
bridge outputs to tri-state (high-impedance off-state).
Features
• 5.0 to 28 V continuous operation (transient operation from 5.0 to
40 V)
• 235 mΩ maximum R
DS(ON)
@ T
J
=150 °C (each H-bridge
MOSFET)
• 3.0 V and 5.0 V TTL / CMOS logic compatible inputs
• Overcurrent limiting (regulation) via internal constant-off-time
PWM
• Output short-circuit protection (short to VPWR or GND)
• Temperature-dependant current-limit threshold reduction
• All inputs have an internal source/sink to define the default
(floating input) states
• Sleep mode with current draw < 12 µA
V
DD
34931
Industrial
H-BRIDGE
EK SUFFIX (PB-FREE)
98ARL10543D
32-PIN SOICW-EP
ORDERING INFORMATION
Device
(Add R2 Suffix for
Tape and Reel)
MC34931EK
Temperature
Range (T
A
)
-40 to 85 °C
Package
32 SOICW-EP
V
PWR
34931
SF
FB
VPWR
CCP
OUT1
IN1
IN2
OUT2
D1
EN/D2
PGND
AGND
MOTOR
MCU
Figure 1. MC34931 Simplified Application Diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2013. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VPWR
LOGIC SUPPLY
VDD
CCP
VCP CHARGE
PUMP
TO GATES
HS1
HS1
HS2
OUT1
OUT2
LS1
LS2
IN1
IN2
EN/D2
D1
SF
FB
AGND
GATE DRIVE
AND
PROTECTION
LOGIC
LS1
HS2
LS2
VSENSE
ILIM PWM
PGND
CURRENT MIRROR
AND
CONSTANT OFF-TIME
PWM CURRENT REGULATOR
PGND
Figure 2. 34931 Simplified Internal Block Diagram
34931
2
Analog Integrated Circuit Device Data
Freescale Semiconductor
PIN CONNECTIONS
PIN CONNECTIONS
AGND
D1
FB
N/C
EN/D2
N/C
VPWR
VPWR
N/C
OUT1
OUT1
N/C
N/C
N/C
PGND
PGND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
SF
IN1
N/C
IN2
CCP
N/C
VPWR
VPWR
N/C
OUT2
OUT2
N/C
N/C
N/C
PGND
PGND
32 SOICW-EP
Transparent Top View
Figure 3. 34931 Pin Connections
A functional description of each pin can be found in the Functional Description section beginning on
page 11.
Table 1. 34931 Pin Definitions
Pin
Number
2
3
5
Pin
Name
D1
FB
EN/D2
Pin
Function
Logic Input
Analog
Output
Logic Input
Formal Name
Disable Input 1
(Active High)
Feedback
Enable Input
Definition
When D1 is logic HIGH, both OUT1 and OUT2 are tri-stated. Schmitt trigger
input with ~80
μA
source so default condition = disabled.
The load current feedback output provides ground referenced 0.24% of the
high side output current. (Tie to GND through a resistor if not used.)
When EN/D2 is logic HIGH the H-bridge is operational. When EN/D2 is logic
LOW, the H-bridge outputs are tri-stated and placed in Sleep mode. (logic
input with ~ 80
μA
sink so default condition = Sleep mode.)
These pins must be connected together physically as close as possible and
directly soldered down to a wide, thick, low resistance supply plane on the
PCB.
Source of HS1 and drain of LS1.
High-current power ground pins must be connected together physically as
close as possible and directly soldered down to a wide, thick, low resistance
ground plane on the PCB.
Source of HS2 and drain of LS2.
External reservoir capacitor connection for the internal charge pump;
connected to VPWR. Allowable values are 30 nF to 100 nF.
Note:
This
capacitor is required for the proper performance of the device.
7, 8, 25, 26
VPWR
Power Input
Positive Power
Supply
H-bridge Output 1
Power Ground
10, 11
15-18
OUT1
PGND
Power
Output
Power
Ground
Power
Output
Analog
Output
22, 23
28
OUT2
CCP
H-bridge Output 2
Charge Pump
Capacitor
34931
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
PIN CONNECTIONS
Table 1. 34931 Pin Definitions (continued)
Pin
Number
29
Pin
Name
IN2
Pin
Function
Logic Input
Formal Name
Input 2
Definition
Logic input control of OUT2;e.g., when IN2 is logic HIGH, OUT2 is set to
VPWR, and when IN2 is logic LOW, OUT2 is set to PGND. (Schmitt trigger
Input with ~ 80
μA
source so default condition = OUT2 HIGH.)
Logic input control of OUT1; e.g., when IN1 is logic HIGH, OUT1 is set to
VPWR, and when IN1 is logic LOW, OUT1 is set to PGND. (Schmitt trigger
Input with ~ 80
μA
source so default condition = OUT1 HIGH.)
Open drain active LOW Status Flag output (requires an external pull-up
resistor to V
DD
. Maximum permissible load current < 0.5 mA. Maximum
V
SFLOW
< 0.4 V
@
0.3 mA. Maximum permissible pull-up voltage < 7.0 V.)
The low-current analog signal ground must be connected to PGND via low-
impedance path (<10 mΩ, 0 Hz to 20 kHz).
Pin is not used
31
IN1
Logic Input
Input 1
32
SF
Logic
Output -
Open Drain
Status Flag
(Active Low)
1
4, 6, 9, 12-14,
19-21, 24, 27,
30
EP
AGND
N/C
Analog
Ground
None
Analog Signal
Ground
No Connect
EP
Thermal
Pad
Exposed Pad
Exposed TAB is also the main heatsinking path for the device and must be
connected to GND.
34931
4
Analog Integrated Circuit Device Data
Freescale Semiconductor
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
MAXIMUM RATINGS
Table 2. Maximum Ratings
All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device. These parameters are not production tested.
Ratings
ELECTRICAL RATINGS
Power Supply Voltage
Normal Operation (Steady-state)
Transient Overvoltage
Logic Input Voltage
(2)
SF
Output
(3)
(1)
Symbol
Value
Unit
V
V
PWR(SS)
V
PWR(T)
V
IN
V
SF
I
OUT(CONT)
V
ESD1
V
ESD2
- 0.3 to 28
- 0.3 to 40
- 0.3 to 7.0
- 0.3 to 7.0
5.0
V
V
A
V
± 2000
± 200
±750
±500
Continuous Output Current
(4)
ESD Voltage
(5)
Human Body Model
Machine Model
Charge Device Model
Corner Pins
All Other Pins
THERMAL RATINGS
Storage Temperature
Operating Temperature
(6)
Ambient
Junction
Peak Package Reflow Temperature During Reflow
(7),(8)
Approximate Junction-to-Case Thermal Resistance
(9)
T
STG
T
A
T
J
T
PPRT
R
θJC
- 65 to 150
°
C
°
C
- 40 to 85
- 40 to 150
Note 8
< 1.0
°C
°
C/W
Notes
1. Device survives repetitive transient overvoltage conditions for durations not to exceed 500 ms
@
duty cycle not to exceed 5.0%. External
protection is required to prevent device damage in case of a reverse power condition.
2. Exceeding the maximum input voltage on IN1, IN2, EN/D2 or D1 may cause a malfunction or permanent damage to the device.
3. Exceeding the pull-up resistor voltage on the open drain
SF
pin may cause permanent damage to the device.
4. Continuous output current capability is dependent on sufficient package heatsinking to keep junction temperature
≤
150
°
C.
5. ESD testing is performed in accordance with the Human Body Model (C
ZAP
= 100 pF, R
ZAP
= 1500
Ω),
Machine Model (C
ZAP
= 200 pF,
R
ZAP
= 0
Ω),
and the Charge Device Model (CDM), Robotic (C
ZAP
= 4.0 pF).
6.
The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking provided. Brief
non-repetitive excursions of junction temperature above 150
°
C can be tolerated, provided the duration does not exceed 30 seconds
maximum. (Non-repetitive events are defined as not occurring more than once in 24 hours.)
Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may
cause malfunction or permanent damage to the device.
Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.
Exposed heatsink pad plus the power and ground pins comprise the main heat conduction paths. The actual R
θ
JB
(junction-to-PC board)
values varies depending on solder thickness and composition and copper trace thickness and area. Maximum current at maximum die
temperature represents ~16 W of conduction loss heating in the diagonal pair of output MOSFETs. Therefore, the R
θ
JA
must be
< 5.0
°C/W
for maximum current at 70
°C
ambient. Module thermal design must be planned accordingly.
7.
8.
9.
34931
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
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